QP7025 Doc QP7025 rev 0.doc QP7025 High-Speed 8K x 16 Dual-Port Static RAM General Description The QP7025 is a CMOS Fast 8K x 16 Dual-Port Static RAM (SRAM). QP Semiconductor designed the QP7025 to be a direct replacement for the IDT7025. It is designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or larger (wider) word systems. Applications requiring a 32-bit or wider memory system can use the MASTER/SLAVE Dual-Port RAM approach to achieve full-speed, error free operation without additional discrete logic. The QP7025 supports asynchronous access for reads or writes to any location in memory via two independent ports with separate control, address, and I/O pins that function identically to the IDT7025 that it replaces. The QP7025 has an automatic power down feature controlled by the appropriate Chip Enable (CE) pin that puts each port in a very low standby power mode. The QP7025 utilizes CMOS high-performance technology which allows the devices to typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 10W from a 2V source. The QP7025 is available in a hermetic ceramic 84-pin PGA and a ceramic 84-pin Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Features - True Dual-Ported memory cells which allow simultaneous reads of the same memory location - High-speed access o Military: 35/45/55/70ns o Industrial: 20/25ns - Low-power operation o QP7025S Active: 750mW (typ.) Standby: 0.2mW (typ.) o QP7025L Active: 750mW (typ.) Standby: 0.2mW (typ.) - Separate upper-byte and lower-byte control for multiplexed bus compatibility - Expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device o M/S = H for BUSY output flag on Master o M/S = L for BUSY input on Slave o Interrupt Flag o On-chip port arbitration logic - Full on-chip hardware support of semaphore signaling between ports - Fully asynchronous operation from either port - Battery backup operation2V data retention - TTL-compatible, single 5V (10%) power supply - Packages: 84-pin PGA & 84-pin Flatpack - Industrial temperature range (40C to +85C) is available 2945 Oakmead Village Ct, Santa Clara, CA 95051 Phone: (408) 737-0992 Fax: (408) 7368708 Internet: www.qpsemi.com QP7025 Block Diagram Notes: (Master): BUSY is output (Slave): BUSY is input. Outputs and INT outputs are non-tri-stated push-pull. Functional Description Left Port Right Port Functional Description Chip Enable CE CE L R Read/Write Enable R/ W R/W L R Output Enable OE OE L R A A A A Address 0L 12L 0R 12R I/O I/O I/O I/O Data Input/Output 0L 15L 0R 15R SEM SEM Semaphore Enable L R Upper Byte Select UB UB L R Lower Byte Select LB LB L R Interrupt Flag INT INT L R Busy Flag BUSY BUSY L R Master Slave Select M / S Power- All V pins must be connected to a power supply CC V CC Ground- All GND pins must be connected to a good ground GND QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051 Page 2 of 21