TISP8250D UNIDIRECTIONAL P-GATE THYRISTOR OVERVOLTAGE AND OVERCURRENT PROTECTOR TISP8250D Overvoltage and Overcurrent Protector Telecommunication System 30 A 10/1000 Protector Agency Recognition Ion-Implanted Breakdown Region Description - Precise and Stable Voltage UL File Number: E215609 V V DRM (BO) Device Name V V 8-SOIC Package (Top View) TISP8250D 250340 G 1 8 A Rated for International Surge Wave Shapes NC 2 7 A I PPSM Wave Shape Standard A NC 3 6 A 2/10 GR-1089-CORE 75 K 4 5 A 0.5/700CNET I 31-24 40 MD8XAAA 10/700 ITU-T K.20/21 40 NC - No internal connection 10/1000 GR-1089-CORE30 Device Symbol A Functional Replacement for TPP25011 ................................................... UL Recognized Component Description The TISP8250D is a P-gate reverse-blocking thyristor (SCR) designed for the protection of telecommunications equipment against overvoltages and overcurrents on the telephone line G caused by lightning, a.c. power contact and induction. The fixed voltage and current triggered modes make the TISP8250D SD8XAA particularly suitable for the protection of ungrounded customer K premise equipment. Connected across the d.c. side of a telephone set polarity bridge, in fixed voltage mode these devices can protect the ringer in the on-hook condition. In an off-hook condition, either the fixed voltage or curr ent triggered modes can protect the following telephone electronics. Without external gate activation, the TISP8250D is a fixed voltage protector. The maximum working voltage without clipping is 250 V and the protection voltage is 340 V. Lower values of protection voltage may be set by connecting an avalanche breakdown diode of less than 250 V between the TISP8250D gate and anode (see Figure 2.) By connecting a small value resistor in series with the line conductor and connecting the TISP8250D gate cathode terminals in parallel with the resistor, conductor overcurrents can gate trigger the TISP8250D into conduction. Overvoltages are initially clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. Overcurrents develop sufficient voltage across the external gate-cathode resistor to trigger the device into a low- voltage on state. This low-voltage on state causes the current resulting from the overstress to be safely diverted through the device. The high crowbar holding current helps prevent d.c. latchup as the diverted current subsides. How To Order Marking Standard Device PackageCarrier Order As Code Quantity TISP8250D 8-SOIC Embossed Tape Reeled TISP8250DR-S 8250 2500 JULY 2000 REVISED JULY 2019 *RoHS Directive 2015/863, Mar 31, 2015 and Annex. Specifications are subject to change without notice. Users should verify actual device performance in their WARNING Cancer and Reproductive Harm specific applications. The products described herein and this document are subject to specific legal disclaimers as www.P65Warnings.ca.gov set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf. TISP8250D Overvoltage and Overcurrent Protector Absolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) A Rating Symbol Value Unit Repetitive peak off-state voltage (see Note 1) V 250 V DRM Non-repetitive peak impulse current (see Notes 2, 3 and 4) 75 2/10 s (Telcordia GR-1089-CORE, 2/10 s waveshape) 40 0.2/310 (CNET I 31-24, 0.5/700 s waveshape) I 40 A 5/310 s (ITU-T K.20/21, 10/700 s voltage waveshape) PPSM 40 5/310 s (FTZ R12, 10/700 s voltage waveshape) 30 10/1000 s (Telcordia GR-1089-CORE, 10/1000 s voltage waveshape) Non-repetitive peak on-state current, 50 Hz (see Notes 2, 3 and 4) 5 10 ms half sine wave I 3.5 A 1s rectified sine wave TSM 0.7 1000 s rectified sine wave Junction temperature T -40 to +150 C J Storage temperature range T -65 to +150 C stg NOTES: 1. For voltage values at lower temperatures, derate at 0.13 %/ C. 2. Initially the device must be in thermal equilibrium, with T = 25 C. J 3. The surge may be repeated after the device returns to its initial conditions. 4. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A printed wiring track widths. Derate current values at -0.61 %/C for ambient temperatures above 25 C. Electrical Characteristics, T = 25 C (Unless Otherwise Noted) A Parameter Test Conditions Min Typ Max Unit T = 25 C 5 A I Repetitive peak off-state current V = V A DRM D DRM T = 85 C 10 A V Breakover voltage dv/dt = 250 V/ms, R = 300 340 V (BO) SOURCE I Breakover current dv/dt = 250 V/ms, R = 300 15 200 mA (BO) SOURCE I Holding current I = 5 A, di/dt = -30 mA/ms 180 mA H T V Gate-cathode voltage I = 30 mA 0.6 1.2 V GK G I Gate trigger current V =100 V 40 mA GT AK I Off-state current V =60V 5 A D D C Off-state capacitance f = 1 MHz, V = 1 V rms, V = 5 V 100 pF O d D Thermal Characteristics, T = 25 C (Unless Otherwise Noted) A Parameter Test Conditions Min Typ Max Unit EIA/JESD51-3 PCB, I = I T TSM(1000) R Junction to ambient thermal resistance 170 C/W JA (see Note 5) NOTE 5. EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5A rated printed wiring track widths. Asia-Pacific: Tel: +886-2 2562-4117 Email: asiacus bourns.com Europe: Tel: +36 88 885 877 Email: eurocus bourns.com The Americas: Tel: +1-951 781-5500 Email: americus bourns.com www.bourns.com JULY 2000 REVISED JULY 2019 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.