MAX9323 19-2575 Rev 0 10/02 One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver General Description Features The MAX9323 low-skew, low-jitter, clock and data dri- 1.7ps Added Random Jitter RMS ver distributes one of two single-ended LVCMOS inputs 150ps (max) Part-to-Part Skew to four differential LVPECL outputs. A single logic con- trol signal (CLK SEL) selects the input signal to distrib- 11ps Output-to-Output Skew ute to all outputs. The device operates from 3.0V to 450ps Propagation Delay 3.6V, making the device ideal for 3.3V systems, and consumes only 25mA (max) of supply current. Pin Compatible with ICS8535-01 The MAX9323 features low 150ps part-to-part skew, low Consumes Only 25mA (max) Supply Current 11ps output-to-output skew, and low 1.7ps RMS jitter, (50% Less than ICS8535-01) making the device ideal for clock and data distribution across a backplane or board. All outputs are enabled Synchronous Output Enable/Disable and disabled synchronously with the clock input to pre- Two Selectable LVCMOS Inputs vent partial output clock pulses. 3.0V to 3.6V Supply Voltage Range The MAX9323 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm 4mm thin QFN -40C to +85C Operating Temperature Range packages and operates over the extended (-40C to +85C) temperature range. The MAX9323 is pin com- patible with Integrated Circuit Systems ICS8535-01. Ordering Information Applications PART TEMP RANGE PIN-PACKAGE Precision Clock Distribution MAX9323EUP -40C to +85C 20 TSSOP Low-Jitter Data Repeater MAX9323ETP* -40C to +85C 20 Thin QFN-EP** *Future productContact factory for availability. Data and Clock Driver and Buffer **EP = Exposed paddle. Central-Office Backplane Clock Distribution Functional Diagram and Typical Operating Circuit appear at DSLAM Backplane end of data sheet. Base Station Hubs Pin Configurations TOP VIEW 20 19 18 17 16 GND 1 20 Q0 CLK EN 2 19 Q0 15 V CLK0 1 CC CLK SEL 3 18 V CC Q1 N.C. 2 14 CLK0 4 17 Q1 MAX9323 CLK1 3 13 Q1 MAX9323 N.C. 5 16 Q1 **EXPOSED PADDLE 4 12 N.C. Q2 CLK1 6 15 Q2 N.C. 5 11 Q2 N.C. 7 14 Q2 N.C. 8 13 V CC 6789 10 N.C. 9 12 Q3 V 10 11 Q3 CC THIN QFN-EP** (4mm x 4mm) TSSOP **CONNECT EXPOSED PADDLE TO GND. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. CLK SEL N.C. CLK EN V CC GND Q3 Q0 Q3 V Q0 CCOne-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver ABSOLUTE MAXIMUM RATINGS V to GND...........................................................-0.3V to +4.0V Junction-to-Case Thermal Resistance CC Q , Q , CLK , CLK SEL, 20-Pin TSSOP ............................................................+20C/W CLK EN to GND.....................................-0.3V to (V + 0.3V) 20-Pin 4mm 4mm Thin QFN......................................+2C/W CC Continuous Output Current.................................................50mA Operating Temperature Range ...........................-40C to +85C Surge Output Current........................................................100mA Junction Temperature......................................................+150C Continuous Power Dissipation (T = +70C) Storage Temperature Range .............................-65C to +150C A 20-Pin TSSOP (derate 11mW/C)..............................879.1mW Soldering Temperature (10s)...........................................+300C 20-Pin 4mm 4mm Thin QFN (derate 16.9mW/C)...1349.1mW Junction-to-Ambient Thermal Resistance in Still Air 20-Pin TSSOP ............................................................+91C/W 20-Pin 4mm 4mm Thin QFN.................................+59.3C/W Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V, outputs terminated with 50 1% to (V - 2V), CLK SEL = V or GND, CLK EN = V , T = -40C to +85C, CC CC CC CC A unless otherwise noted. Typical values are at V = 3.3V, T = +25C.) (Notes 1, 2, and 3) CC A PARAMETER SYMB O L CONDITIONS MINTYPMAXUNITS INPUTS (CLK0, CLK1, CLK SEL, CLK EN) CLK0, CLK1 2 V CC Input High Voltage V Figure 1 V IH CLK EN, CLK SEL 2 V CC CLK0, CLK1 0 1.3 Input Low Voltage V Figure 1 V IL CLK EN, CLK SEL 0 0.8 CLK0, CLK1, CLK SEL = V 150 CC Input High Current I A IH CLK EN = V -5 +5 CC CLK0, CLK1, CLK SEL = GND -5 +5 Input Low Current I A IL CLK EN = GND -150 Input Capacitance C CLK0, CLK1, CLK SEL, CLK EN (Note 4) 4 pF IN OUTPUTS (Q , Q ) Single-Ended Output High V - V - CC CC V Figure 1 V OH Voltage 1.4 1.0 Single-Ended Output Low V - V - CC CC V Figure 1 V OL Voltage 2.0 1.7 Differential Output Voltage V Figure 1, V = V - V 0.6 0.85 V OD OD OH OL SUPPLY Supply Current (Note 5) I 25 mA CC 2 MAX9323