LTC6954 Low Phase Noise, Triple Output Clock Distribution Divider/Driver Fea T Descrip T n Low Noise Clock Distribution: Suitable for High The LTC 6954 is a family of very low phase noise clock Speed/High Resolution ADC Clocking distribution parts. Each part has three outputs and each n Additive Jitter < 20fs (12kHz to 20MHz) output has an individually programmable frequency RMS n Additive Jitter < 85fs (10Hz to Nyquist) divider and delay. There are four members of the family, RMS n 1.8GHz Maximum Input Frequency differing in their output logic signal type: (LTC6954-1 When DELAY = 0) LTC6954-1: Three LVPECL outputs n 1.4GHz Maximum Input Frequency LTC6954-2: Two LVPECL and one LVDS/CMOS outputs (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) n LTC6954-3: One LVPECL and two LVDS/CMOS outputs EZSync Clock Synchronization Compatible n Three Independent, Low Noise Outputs LTC6954-4: Three LVDS/CMOS outputs n Four Output Combinations Available Each output is individually programmable to divide the n Three Independent Programmable Dividers Covering input frequency by any integer from 1 to 63, and to delay All Integers From 1 to 63 each output by 0 to 63 input clock cycles. The output duty n Three Independent Programmable Delays Covering cycle is always 50%, regardless of the divide number. All Integers From 0 to 63 The LVDS/CMOS outputs are jumper selectable via the n 40C to 105C Junction Temperature Range OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output. a T The LTC6954 also features Linear Technologys EZSync system for perfect clock synchronization and alignment n Clocking High Speed, High Resolution ADCs, DACs every time. and Data Acquisition Systems n Low Jitter Clock Distribution All device settings are controlled through an SPI-compatible L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync serial port. is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 8319551, 8819472. Typical a T Additive Phase Noise vs Offset Frequency, 0.1F 3.3V f = 622.08MHz, Mx 5:0 = 4, IN UP TO 1.4GHz f = 155.52MHz OUTx 120 + + 49.9 IN V LTC6954-3 IN + 130 OUT0 49.9 LVPECL OUTPUT 49.9 DELAY DIVIDE FREQUENCY SYNC OUT0 SYNC 0 TO 63 1 TO 63 UP TO 1.8GHz 140 CONTROL + OUT1 OUT0SEL LVDS OUTPUT DELAY DIVIDE 150 FREQUENCY OUT1 0 TO 63 1 TO 63 OUT1SEL UP TO 1.4GHz 3.3V + OUT2SEL SERIAL OUT2 160 CMOS OUTPUT PORT DELAY DIVIDE SDO FREQUENCY OUT2 AND 0 TO 63 1 TO 63 UP TO 250MHz DIGITAL 170 SDI SPI SERIAL SCLK PORT 180 CS 10 100 1k 10k 100k 1M 10M GND 6954 TA01a OFFSET FREQUENCY (Hz) 6954 TA01b 6954f 1 For more information www.linear.com/LTC6954 ADDITIVE PHASE NOISE (dBc/Hz) ion pplica ions pplica ion uresLTC6954 a Te Maxi Mu M r a T p c F T (Note 1) Supply Voltages TOP VIEW + + + + + (V , V , V , V , V and A D IN OUT0 OUT1 + V to GND) ........................................................3.6V OUT2 LTC6954-1, -2, -3 LVPECL Outputs 36 35 34 33 32 31 + + + V 1 30 V OUTx Output Voltage High ......................V + 0.3V OUT2 IN OUT OUT2 2 29 GND OUTx Output Voltage Low ..................... Source 25mA + OUT2 28 IN 3 LTC6954-2, -3, -4 LVDS/CMOS Outputs + + V 4 27 IN + OUT2 OUTx ..........................................0.3V to (V +0.3V) A + V 5 GND 26 OUT1 TEMP Input Current ...............................................10mA + OUT1 6 25 V IN 37 TEMP Low Voltage ................................................0.3V + GND + OUT1 V 7 24 A + + + Voltage on All Other Pins ..............0.3V to (V + 0.3V) A V 8 23 V OUT1 A + Operating Junction Temperature Range, T (Note 2) V SYNC 9 22 J OUT0 + OUT0 10 21 V LTC6954I ............................................... 40C to 105C D + OUT0 SDI 11 20 Junction Temperature, T ................................ 150C JMAX + V 12 19 SCLK OUT0 Storage Temperature Range .................. 65C to 150C 13 14 15 16 17 18 UFF PACKAGE 36-LEAD (4mm 7mm) PLASTIC QFN 0.5mm LEAD PITCH T = 150C, = 2C/W, = 18C/W JMAX JCbottom JCtop EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB GND o r D i n F Ma T LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE LTC6954IUFF-1 PBF LTC6954IUFF-1 TRPBF 69541 36-Lead (4mm 7mm) Plastic QFN 40C to 105C LTC6954IUFF-2 PBF LTC6954IUFF-2 TRPBF 69542 36-Lead (4mm 7mm) Plastic QFN 40C to 105C LTC6954IUFF-3 PBF LTC6954IUFF-3 TRPBF 69543 36-Lead (4mm 7mm) Plastic QFN 40C to 105C LTC6954IUFF-4 PBF LTC6954IUFF-4 TRPBF 69544 36-Lead (4mm 7mm) Plastic QFN 40C to 105C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part markings, go to: