SHARC+ Single Core High Performance DSP (Up to 1 GHz) ADSP-21562/21563/21565/21566/21567/21569 SYSTEM FEATURES MEMORY Enhanced SHARC+ high performance floating-point core Large on-chip Level 2 (L2) SRAM with ECC protection, up to 8Mb (1 MB) Up to 1 GHz One Level 3 (L3) interface optimized for low system power, 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity providing 16-bit interface to DDR3/DDR3L SDRAM devices (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support ADDITIONAL FEATURES 32-bit fixed point Security and Protection Byte, short word, word, long word addressed Crypto hardware accelerators Powerful DMA system Fast secure boot with IP protection On-chip memory protection Enhanced FIR and IIR accelerators running up to 1 GHz Integrated safety features AEC-Q100 qualified for automotive applications 17 mm 17 mm, 400-ball CSP BGA (0.8 mm pitch), RoHS APPLICATIONS compliant 120-lead LQFP EP (0.4 mm pitch), RoHS compliant Automotive: audio amplifier, head unit, ANC/RNC, rear seat Low system power across automotive temperature range entertainment, digital cockpit, ADAS Consumer: speakers, sound bars, AVRs, conferencing sys- tems, mixing consoles, microphone arrays, headphones SYSTEM CONTROL SECURITY AND PROTECTION SHARC+ CORE SYSTEM PROTECTION UNIT (SPU) UP TO SYSTEM MEMORY 1 GHz PROTECTION UNIT (SMPU) FLOATING-POINT S DSP ENCRYPTION/DECRYPTION PERIPHERALS ACCELERATORS FAULT MANAGEMENT (FMU) SIGNAL ROUTING UNIT (SRU) FIR IIR DUAL CRC (WITH MemDMA) 22 PRECISION CLOCK L1 SRAM (PARITY) GENERATORS (UP TO (UP TO WATCHDOGS 5 Mb (640 kB) 2x DAI 1 GHz) 1 GHz) 24 ASRC FULL SPORT 2x PIN SRAM/CACHE OTP MEMORY PAIRS 24 BUFFER 2428 THERMAL MONITOR UNIT (TMU) 21 S/PDIF Rx/Tx PROGRAM FLOW 2 6 I C SYSTEM EVENT CONTROLLER SYSTEM CROSSBAR AND DMA SUBSYSTEM 1 SPI + 2 QUAD SPI + (SEC) 1 OCTAL SPI TRIGGER ROUTING UNIT (TRU) G 3 UARTs P I 2240 2 LINK PORTS O CLOCK, RESET, AND POWER L3 MEMORY SYSTEM CLOCK GENERATION UNIT (CGU) 10 TIMERS + 1 COUNTER INTERFACES L2 MEMORY CLOCK DISTRIBUTION UNIT (CDU) MLB 3-PIN DDR3/DDR3L RESET CONTROL UNIT (RCU) SRAM HADC (4 CHAN, 12-BIT) (ECC) BGA ONLY 24 DYNAMIC POWER MANAGEMENT UP TO 8 Mb (1 MB) (DPM) 16 DEBUG UNIT DATA TM Arm CoreSight DEBUG AND TRACE SYSTEM WATCHPOINT UNIT (SWU) Figure 1. ADSP-21569 (Full-Featured Model) Processor Block Diagram SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2021 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-21562/21563/21565/21566/21567/21569 TABLE OF CONTENTS System Features ....................................................... 1 Specifications ........................................................ 45 Memory ................................................................ 1 Operating Conditions ........................................... 45 Additional Features .................................................. 1 Electrical Characteristics ....................................... 48 Applications ........................................................... 1 HADC .............................................................. 52 Table of Contents ..................................................... 2 TMU ................................................................ 52 Revision History ...................................................... 3 Absolute Maximum Ratings ................................... 53 General Description ................................................. 4 ESD Caution ...................................................... 53 SHARC Processor ................................................. 5 Timing Specifications ........................................... 54 SHARC+ Core Architecture .................................... 7 Output Drive Currents ......................................... 87 System Infrastructure ............................................. 9 Test Conditions .................................................. 88 System Memory Map ............................................. 9 Environmental Conditions .................................... 89 Security Features ................................................ 12 ADSP-2156x 400-Ball BGA Ball Assignments ................ 91 Security Features Disclaimer .................................. 13 Numerical by Ball Number .................................... 91 Safety Features ................................................... 13 Alphabetical by Pin Name ..................................... 94 Processor Peripherals ........................................... 14 Configuration of the 400-Ball CSP BGA ................... 97 System Acceleration ............................................ 17 ADSP-2156x 120-Lead LQFP Lead Assignments ............ 98 System Design .................................................... 17 Numerical by Lead Number ................................... 98 System Debug .................................................... 19 Alphabetical by Pin Name ..................................... 99 Development Tools ............................................. 20 Configuration of the 120-Lead LQFP Lead Configuration ................................................ 100 Additional Information ........................................ 21 Outline Dimensions .............................................. 101 Related Signal Chains .......................................... 21 Surface-Mount Design ........................................ 102 ADSP-2156x Detailed Signal Descriptions ................... 22 Automotive Products ............................................ 103 400-Ball CSP BGA Signal Descriptions ....................... 25 Planned Automotive Production Products .................. 103 GPIO Multiplexing for 400-Ball CSP BGA Package ....... 31 Planned Production Products .................................. 104 120-Lead LQFP Signal Descriptions ........................... 33 Ordering Guide ................................................... 104 GPIO Multiplexing for 120-Lead LQFP Package ............ 36 ADSP-2156x Designer Quick Reference ...................... 37 Rev. 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