Integrated Power Solution with Quad Low Noise Buck Regulators Data Sheet ADP5014 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.75 V to 6.0 V ADP5014 VREF R RT Programmable output voltage range: 0.5 V to 0.9 PVINx RT C1 OSC REF Low output noise: ~25 V rms when V V OUT REF EN1/ENALL CFG1 EN2/DL12 1.0% output accuracy over full temperature range CFG2 LOGIC DECODER EN3/UV 500 kHz to 2.5 MHz adjustable switching frequency GPIO EN4/DL34 Power regulation AVIN FB1 2.75V TO 6.0V PVIN1 Channel 1 and Channel 2: programmable 2 A/4 A sync SW1 C2 L1 buck regulators, or single 8 A output in parallel PVIN1 CH 1 VOUT1 LOW-NOISE BUCK VREF VSET1 (2A/4A) Channel 3 and Channel 4: programmable 1 A/2 A sync C3 PGND1 buck regulators, or single 4 A output in parallel COMP1 Flexible parallel operation FB2 Precision enable with 0.6 V threshold PVIN2 SW2 Manual or sequence mode for power-up and power-down C4 CH 2 L2 VOUT2 LOW-NOISE BUCK VREF sequence VSET2 (2A/4A) C5 PGND2 Selective FPWM or PSM operation mode COMP2 Precision undervoltage comparator Frequency synchronization input or output PVIN3 L3 VOUT3 SW3 Active output discharge switch C6 FB3 C7 CH 3 VREF VSET3 Power-good flag on selective channels via factory fuse LOW-NOISE BUCK (1A/2A) PGND3 UVLO, OVP, OCP, and TSD protection COMP3 40-lead, 6 mm 6 mm LFCSP package PVIN4 L4 VOUT4 40C to +125C junction temperature SW4 C8 FB4 C9 CH 4 VREF VSET4 APPLICATIONS LOW-NOISE BUCK (1A/2A) PGND4 COMP4 RF transceiver, high speed analog-to-digital converter (ADC)/digital-to-analog converter (DAC), mixed signal ASIC FPGA and processor applications AGND EXPOSED PAD Security and surveillance Figure 1. Medical applications GENERAL DESCRIPTION The ADP5014 combines four high performance, low noise The ADP5014 features two enable modes. The manual mode buck regulators in a 40-lead LFCSP package. Relying on its low has four individual precision enable pins to enable each output noise (~25 V rms when VOUT VREF), the low noise regulator manually. Alternatively, the sequence mode has one buck regulator enables the powering up of the noise sensitive grouped precision enable signal with programmable power-up signal chain products. and power-down delay timers on each rail for specific rail sequence requirements. All channels in the ADP5014 integrate high-side and low-side power metal-oxide semiconductor field effect transistors The switching frequency of the ADP5014 can be programmed (MOSFET). Channel 1 and Channel 2 deliver a programmable or synchronized to an external clock from 500 kHz to 2.5 MHz. output current of 2 A or 4 A. Combining Channel 1 and The ADP5014 offers other key features like selective forced Channel 2 in a parallel configuration provides a single output pulse width modulation (FPWM)/power saving mode (PSM), with up to 8 A of current. an undervoltage output (UVO), active output discharge, and a Channel 3 and Channel 4 deliver a programmable output current power-good flag. Other safety features include input under- of 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallel voltage lockout (UVLO), overvoltage protection (OVP), configuration can provide a single output with up to 4 A of overcurrent protection (OCP) and thermal shutdown (TSD). current. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15496-001ADP5014 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overvoltage Protection .............................................................. 20 Applications ....................................................................................... 1 Undervoltage Lockout ............................................................... 20 Typical Application Circuit ............................................................. 1 Active Output Discharge Switch .............................................. 21 General Description ......................................................................... 1 Thermal Shutdown .................................................................... 21 Revision History ............................................................................... 2 Applications Information .............................................................. 22 Detailed Functional Block Diagram .............................................. 3 ADIsimPower Design Tool ....................................................... 22 Specifications ..................................................................................... 4 Programming the Output Voltage ........................................... 22 Buck Regulator Specifications .................................................... 5 Voltage Conversion Limitations ............................................... 22 Absolute Maximum Ratings ............................................................ 7 Current-Limit Setting ................................................................ 23 Thermal Resistance ...................................................................... 7 Soft Start Setting ......................................................................... 23 ESD Caution .................................................................................. 7 Inductor Selection ...................................................................... 23 Pin Configuration and Function Descriptions ............................. 8 Output Capacitor Selection ....................................................... 24 Typical Performance Characteristics ........................................... 10 Input Capacitor Selection .......................................................... 24 Theory of Operation ...................................................................... 14 Programming the UVLO Input ................................................ 24 Buck Regulator Operational Modes ......................................... 14 Compensation Components Design ....................................... 24 Low Noise Architecture ............................................................. 14 Power Dissipation....................................................................... 25 Internal Reference (VREF) ........................................................ 14 Junction Temperature ................................................................ 26 Adjustable Output Voltage ........................................................ 14 Design Examples ............................................................................ 27 Function Configurations (CFG1 and CFG2) ......................... 15 Setting the Switching Frequency .............................................. 27 Parallel Operation....................................................................... 16 Setting the Output Voltage ........................................................ 27 Manual/Sequence Mode ............................................................ 16 Setting the Configuations (CFG1 and CFG2) ........................ 27 General Purpose Input/Output (GPIO) .................................. 18 Selecting the Inductor ................................................................ 27 Oscillator ..................................................................................... 18 Selecting the Output Capacitor ................................................ 28 Synchronization Input/Output ................................................. 19 Designing the Compensation Network ................................... 28 Power-Good Function ............................................................... 19 Low Noise Output Design ......................................................... 28 UV Comparator (Sequence Mode Only) ................................ 19 PCB Layout Recommendations .................................................... 30 Soft Start ...................................................................................... 20 Typical Application Circuits ......................................................... 31 Startup with Precharged Output .............................................. 20 Factory Programmable Options ................................................... 33 Current-Limit Protection .......................................................... 20 Factory Default Options ............................................................ 33 Frequency Fold Back .................................................................. 20 Outline Dimensions ....................................................................... 34 Short-Circuit Protection (SCP) ................................................ 20 Ordering Guide .......................................................................... 34 REVISION HISTORY 8/2019Rev. 0 to Rev. A 6/2017Revision 0: Initial Version Changes to Parallel Operation Section ........................................ 16 Updated Outline Dimensions ....................................................... 34 Rev. A Page 2 of 34