Synchronous Buck Controller with Constant On Time and Valley Current Mode Data Sheet ADP1878/ADP1879 FEATURES TYPICAL APPLICATIONS CIRCUIT V = 2.95V TO 20V IN Power input voltage range: 2.95 V to 20 V On-board bias regulator VIN Minimum output voltage: 0.6 V C C ADP1878/ 0.6 V reference voltage with 1.0% accuracy C C IN C2 ADP1879 R C Supports all N-channel MOSFET power stages COMP BST C 10k Available in 300 kHz, 600 kHz, and 1.0 MHz options BST Q1 V L REG EN DRVH R TOP V No current sense resistor required OUT V OUT FB SW C OUT Power saving mode (PSM) for light loads (ADP1879 only) R BOT LOAD Q2 GND DRVL Resistor programmable current limit C VREG2 VREG Power good with internal pull-up resistor C VREG R PGD PGOOD V EXT Externally programmable soft start RES SS R Thermal overload protection RES C SS PGND Short-circuit protection Standalone precision enable input Figure 1. Integrated bootstrap diode for high-side drive Starts into a precharged output Available in a 14-lead LFCSP WD package APPLICATIONS Telecommunications and networking systems Mid-to-high end servers Set-top boxes DSP core power supplies conditions. The low-side current sense, current gain scheme and GENERAL DESCRIPTION integration of a boost diode, together with the PSM/forced The ADP1878/ADP1879 are versatile current-mode, synchronous pulse-width modulation (PWM) option, reduce the external step-down controllers. They provide superior transient response, device count and improve efficiency. optimal stability, and current-limit protection by using a constant The ADP1878/ADP1879 operate over the 40C to +125C on time, pseudo fixed frequency with a programmable current-limit, current control scheme. These devices offer optimum performance junction temperature range and are available in a 14-lead at low duty cycles by using a valley, current-mode control architec- LFCSP WD package. ture allowing the ADP1878/ADP1879 to drive all N-channel power 100 V = 5V (PSM) 95 IN stages to regulate output voltages to as low as 0.6 V. 90 The ADP1879 is the power saving mode (PSM) version of the 85 80 device and is capable of pulse skipping to maintain output 75 regulation while achieving improved system efficiency at light 70 V = 16.5V IN loads (see the ADP1879 Power Saving Mode (PSM) section for 65 V = 13V more information). IN 60 55 V = 13V (PSM) IN Available in three frequency options (300 kHz, 600 kHz, and T = 25C 50 A V = 1.8V OUT 1.0 MHz) plus the PSM option, the ADP1878/ADP1879 are well 45 f = 300kHz SW V = 16.5V (PSM) 40 IN suited for a wide range of applications that require a single input WRTH INDUCTOR: 35 744325120, L = 1.2H, DCR = 1.8m power supply range from 2.95 V to 20 V. Low voltage biasing is INFINEON FETs: 30 BSC042N03MS G (UPPER/LOWER) supplied via a 5 V internal low dropout regulator (LDO). In 25 10 100 1k 10k 100k addition, soft start programmability is included to limit input LOAD CURRENT (mA) inrush current from the input supply during startup and to Figure 2. ADP1878/ADP1879 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz) provide reverse current protection during precharged output Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112012 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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EFFICIENCY (%) 09441-102 09441-001ADP1878/ADP1879 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pseudo Fixed Frequency............................................................ 22 Applications ....................................................................................... 1 Power-Good Monitoring ........................................................... 23 Typical Applications Circuit ............................................................ 1 Applications Information .............................................................. 24 General Description ......................................................................... 1 Feedback Resistor Divider ........................................................ 24 Revision History ............................................................................... 2 Inductor Selection ...................................................................... 24 Specifications ..................................................................................... 3 Output Ripple Voltage (V ) .................................................. 24 RR Absolute Maximum Ratings ....................................................... 5 Output Capacitor Selection....................................................... 24 Thermal Resistance ...................................................................... 5 Compensation Network ............................................................ 25 ESD Caution .................................................................................. 5 Efficiency Consideration ........................................................... 26 Pin Configuration and Function Descriptions ............................. 6 Input Capacitor Selection .......................................................... 27 Typical Performance Characteristics ............................................. 7 Thermal Considerations ............................................................ 27 Theory of Operation ...................................................................... 17 Design Example .......................................................................... 29 Block Diagram ............................................................................ 17 External Component Recommendations .................................... 31 Startup .......................................................................................... 18 Layout Considerations ................................................................... 33 Soft Start ...................................................................................... 18 IC Section (Left Side of Evaluation Board) ............................. 35 Precision Enable Circuitry ........................................................ 18 Power Section ............................................................................. 35 Undervoltage Lockout ............................................................... 18 Differential Sensing .................................................................... 36 On-Board Low Dropout (LDO) Regulator ............................. 18 Typical Application Circuits ......................................................... 37 Thermal Shutdown ..................................................................... 19 12 A, 300 kHz High Current Application Circuit .................. 37 Programming Resistor (RES) Detect Circuit .......................... 19 5.5 V Input, 600 kHz Current Application Circuit ................ 37 Valley Current-Limit Setting .................................................... 19 300 kHz High Current Application Circuit ............................ 38 Hiccup Mode During Short Circuit ......................................... 21 Packaging and Ordering Information ......................................... 39 Synchronous Rectifier ................................................................ 21 Outline Dimensions ................................................................... 39 ADP1879 Power Saving Mode (PSM) ...................................... 21 Ordering Guide .......................................................................... 40 Timer Operation ......................................................................... 22 REVISION HISTORY 9/12Rev. A to Rev. B Changes to Table 7 ........................................................................... 20 6/12Rev. 0 to Rev. A Changes to Table 1 ............................................................................. 3 7/11Revision 0: Initial Version Rev. B Page 2 of 40