Synchronous Buck Controller with Constant On-Time and Valley Current Mode Data Sheet ADP1870/ADP1871 FEATURES TYPICAL APPLICATIONS CIRCUIT V = 2.95V TO 20V IN Power input voltage range: 2.95 V to 20 V On-board bias regulator VIN Minimum output voltage: 0.6 V C C ADP1870/ C IN C C2 0.6 V reference voltage with 1.0% accuracy R ADP1871 C R TOP COMP/EN BST V Supports all N-channel MOSFET power stages OUT C BST Q1 L V Available in 300 kHz, 600 kHz, and 1.0 MHz options FB DRVH OUT R BOT No current-sense resistor required GND SW C OUT Q2 C Power saving mode (PSM) for light loads (ADP1871 only) VREG2 VREG DRVL PGND Resistor-programmable current-sense gain R RES LOAD Thermal overload protection C VREG Short-circuit protection Figure 1. Precision enable input Integrated bootstrap diode for high-side drive 100 Starts into a precharged load V = 5V (PSM) 95 IN Small, 10-lead MSOP and LFCSP packages 90 85 APPLICATIONS 80 75 Telecom and networking systems 70 V = 16.5V IN Mid to high end servers 65 Set-top boxes V = 13V 60 IN DSP core power supplies 55 V = 13V (PSM) IN T = 25C 50 A 12 V input POL supplies V = 1.8V OUT 45 f = 300kHz SW V = 16.5V (PSM) 40 IN WRTH INDUCTOR: 35 744325120, L = 1.2H, DCR = 1.8m GENERAL DESCRIPTION INFINEON FETs: 30 BSC042N03MS G (UPPER/LOWER) The ADP1870/ADP1871 are versatile current-mode, synchronous 25 10 100 1k 10k 100k step-down controllers that provide superior transient response, LOAD CURRENT (mA) optimal stability, and current-limit protection by using a constant Figure 2. Efficiency vs. Load Current (V = 1.8 V, 300 kHz) OUT on-time, pseudo-fixed frequency with a programmable current- limit, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by utilizing valley In addition, an internally fixed soft start period is included to limit current-mode control architecture. This allows the ADP1870/ input in-rush current from the input supply during startup and ADP1871 to drive all N-channel power stages to regulate output to provide reverse current protection during soft start for a pre- voltages as low as 0.6 V. charged output. The low-side current-sense, current-gain scheme and integration of a boost diode, along with the PSM/forced pulse- The ADP1871 is the power saving mode (PSM) version of the width modulation (PWM) option, reduce the external part count device and is capable of pulse skipping to maintain output and improve efficiency. regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1871) The ADP1870/ADP1871 operate over the 40C to +125C section for more information). junction temperature range and are available in a 10-lead MSOP and LFCSP packages. Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well suited for a wide range of applications that require a single-input power supply range from 2.95 V to 20 V. Low voltage biasing is supplied via a 5 V internal LDO. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20102012 Analog Devices, Inc. All rights reserved. EFFICIENCY (%) 08730-001 08730-102ADP1870/ADP1871 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Saving Mode (PSM) Version (ADP1871).................... 22 Applications ....................................................................................... 1 Timer Operation ........................................................................ 22 General Description ......................................................................... 1 Pseudo-Fixed Frequency ........................................................... 23 Typical Applications Circuit ............................................................ 1 Applications Information .............................................................. 24 Revision History ............................................................................... 2 Feedback Resistor Divider ........................................................ 24 Specifications ..................................................................................... 3 Inductor Selection ...................................................................... 24 Absolute Maximum Ratings ............................................................ 5 Output Ripple Voltage (V ) .................................................. 24 RR Thermal Resistance ...................................................................... 5 Output Capacitor Selection....................................................... 24 Boundary Condition .................................................................... 5 Compensation Network ............................................................ 25 ESD Caution .................................................................................. 5 Efficiency Considerations ......................................................... 26 Pin Configuration and Function Descriptions ............................. 6 Input Capacitor Selection .......................................................... 27 Typical Performance Characteristics ............................................. 7 Thermal Considerations ............................................................ 28 ADP1870/ADP1871 Block Diagram ............................................ 18 Design Example .......................................................................... 29 Theory of Operation ...................................................................... 19 External Component Recommendations .................................... 31 Startup .......................................................................................... 19 Layout Considerations ................................................................... 33 Soft Start ...................................................................................... 19 IC Section (Left Side of Evaluation Board) ............................. 37 Precision Enable Circuitry ........................................................ 19 Power Section ............................................................................. 37 Undervoltage Lockout ............................................................... 19 Differential Sensing .................................................................... 38 On-Board Low Dropout Regulator .......................................... 19 Typical Applications Circuits ........................................................ 39 Thermal Shutdown ..................................................................... 20 15 A, 300 kHz High Current Application Circuit .................. 39 Programming Resistor (RES) Detect Circuit .......................... 20 5.5 V Input, 600 kHz Application Circuit ............................... 39 Valley Current-Limit Setting .................................................... 20 300 kHz High Current Application Circuit ............................ 40 Hiccup Mode During Short Circuit ......................................... 21 Outline Dimensions ....................................................................... 41 Synchronous Rectifier ................................................................ 22 Ordering Guide .......................................................................... 42 REVISION HISTORY 7/12Rev. A to Rev. B Changes to Table 2 and Table 3........................................................ 5 Changes to Figure 3 and Table 4 ...................................................... 6 Changed RON = 15 m/100 k Valley Current Level Value from Change to Figure 22 ....................................................................... 10 7.5 to 3.87 Table 7 .......................................................................... 21 Changes to Figure 65 ...................................................................... 18 Updated Outline Dimensions ................................................................. 41 Changes to Efficiency Considerations Section ........................... 26 6/10Rev. 0 to Rev. A Changes to Table 9 ..................................................................................... 28 Added Figure 84 Renumbered Sequentially....................................... 28 Added LFCSP Package ....................................................... Universal Added Figure 96 ......................................................................................... 41 Changes to Applications Section .................................................... 1 Changes to Ordering Guide .................................................................... 42 Changes to Internal Regulator Characteristics Parameter, Table 1 ............................................................................................ 3 3/10Revision 0: Initial Version Rev. B Page 2 of 44