Dual Channel, Configurable, Isolated Digital Input Data Sheet ADE1202 FEATURES GENERAL DESCRIPTION 1 Dual channel, configurable, isolated digital input The ADE1202 is a dual channel, configurable, isolated Programmable trip threshold digital input monitoring solution for energy transmission and On-chip debounce filter distribution applications. The ADE1202 is configured through On-chip data and power Isolation the serial port interface (SPI) to perform an isolated measurement Application circuit monitors wide voltage range of the digital input that is also called binary input or contact 10 V dc to 300 V dc input. The ADE1202 digital output signal on the DOUTx pins 8 V rms to 240 V rms ac (with 10 ms + pickup) reflects the state of the input signal after user configurable Negative dc protected signal conditioning. The SPI protocol supports addressing to Programmable wetting current allow up to eight devices sharing one 4-wire SPI port. Pulse up to 50 mA The ADE1202 application circuit accepts a wide range of input Constant current up to 6.3 mA voltages from 10 V dc to 300 V, or 8 V rms to 240 V rms. The Safety and regulatory approvals programmable wetting current and robust application circuit UL recognition enable the device to meet stringent, system level electromagnetic 3750 V rms for 1 minute per UL 1577 capability (EMC) requirements. CSA Component Acceptance Notice 5A (pending) The ADE1202 includes an isoPower integrated, isolated dc-to-dc CSA 61010-1: 300 V rms converter that eliminates the need for an external isolated power VDE certificate of conformity (pending) supply. The iCoupler chip scale transformer technology is DIN V VDE V 0884-11 (VDE V 0884-11):2017-1 used to isolate the logic signals between the high voltage, V = 565 V peak IORM isolated side and the low voltage, nonisolated side of the EMC robust solution supports relay protection system level digital input monitor. This technology creates a small form requirements factor design that includes data and power isolation. ADC samples available for system diagnostics Internal SAR ADC with PGA An integrated successive approximation register (SAR) Single 3.3 V Supply analog-to-digital converter (ADC) and a programmable gain Integrated isoPower, isolated dc-to-dc converter amplifier (PGA) from 1 to 10 measure the analog inputs. Interfaces The ADC waveforms are available through the SPI port to SPI allow system level diagnostics. DOUTx output reflects state of digital input Note that throughout this data sheet, multifunction pins, such IRQ interrupt pin as DOUT2/IRQ, are referred to either by the entire pin name Operating temperature: 40C to +125C or by a single function of the pin, for example, DOUT2, when 20-lead, LGA package with 6.8 mm creepage only that function is relevant. APPLICATIONS PRODUCT HIGHLIGHTS Energy transmission and distribution 1. Dual channel, configurable, isolated digital input. Multifunction relay protection 2. Single hardware design supports 24 V to 300 V systems. Substation battery monitoring 3. Robust architecture. Bay or substation interlocking 4. Enables system level diagnostics. Merge unit Circuit breaker status indication Remote terminal unit Building automation 1 Protected by U.S. Patent Number 2017/0250043. Other patents pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ADE1202 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Decoupling and Ground Plane Connection ........................... 29 Applications ....................................................................................... 1 Electomagnetic Interface (EMI) Capacitor ............................. 30 General Description ......................................................................... 1 Applications Information .............................................................. 31 Product Highlights ........................................................................... 1 Register Map ................................................................................... 32 Revision History ............................................................................... 2 Register Details ............................................................................... 33 Functional Block Diagram .............................................................. 3 Lock Register ............................................................................... 33 Specif icat ions ..................................................................................... 4 Control Register ......................................................................... 33 Electrical Characteristics ............................................................. 4 Binary Channel Control Register ............................................. 34 Timing Characteristics ................................................................ 6 Binary Channel Threshold Level Register .............................. 35 Insulation and Safety Related Specifications ............................ 7 WARNAx Channel Threshold Level Register ........................ 35 Package Characteristics ............................................................... 7 WARNBx Channel Threshold Level Register ......................... 35 Regulatory Information ............................................................... 8 WARNCx Channel Threshold Level Register ........................ 35 DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Binary Channel Configuration Register ................................. 36 Characteristics .............................................................................. 9 WARNAx Datapath Configuration Register .......................... 36 Absolute Maximum Ratings .......................................................... 10 WARNBx Datapath Configuration Register........................... 36 Thermal Resistance .................................................................... 10 WARNCx Datapath Configuration Register .......................... 36 ESD Caution ................................................................................ 10 Interrupt Mask Register ............................................................. 37 Pin Configuration and Function Descriptions ........................... 11 Interrupt Status Register ............................................................ 37 Typical Performance Characteristics ........................................... 12 Status Register ............................................................................. 38 Test Circuit ...................................................................................... 15 ADC Register .............................................................................. 38 Theory of Operation ...................................................................... 16 ADC Decimated Register .......................................................... 39 Power Supply and Conditioning .............................................. 16 Programmable Load Control Register .................................... 39 Digital Inputs Signal Path .......................................................... 17 Programmable Load Rise Threshold Register ........................ 39 Invalid Mode ............................................................................... 20 Programmable Load Low Code Register ................................ 39 Programmable Load Current .................................................... 20 Programmable Load High Code Register ............................... 40 External FET Protection ............................................................ 22 Programmable Load High Current Period Register .............. 40 Gate Drive .................................................................................... 23 Energy Meter Control Register ................................................ 40 Thermal Shutdown ..................................................................... 24 Energy Meter Maximum Threshold Register ......................... 40 Inter r upt ....................................................................................... 24 Energy Meter Channel 1 Accumulator Register .................... 41 SPI Protocol Overview ............................................................... 24 Energy Meter Channel 2 Accumulator Register .................... 41 Protecting the Integrity of Configuration Registers .............. 27 Programmable Load Enable Register ...................................... 41 Version ......................................................................................... 27 PGA Gain Register ..................................................................... 41 Insulation Wear Out ................................................................... 27 Outline Dimensions ....................................................................... 42 Layout Guidelines ........................................................................... 29 Ordering Guide .......................................................................... 42 Ferrite Bead ................................................................................. 29 REVISION HISTORY 12/2019Revision 0: Initial Version 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