14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9251 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V to 3.3 V output supply SPI SNR ORA 74.3 dBFS at 9.7 MHz input PROGRAMMING DATA D13A 71.5 dBFS at 200 MHz input VIN+A ADC SFDR VINA D0A 93 dBc at 9.7 MHz input DCOA 80 dBc at 200 MHz input VREF Low power SENSE DRVDD 33 mW per channel at 20 MSPS AD9251 REF VCM SELECT 73 mW per channel at 80 MSPS ORB RBIAS Differential input with 700 MHz bandwidth D13B VINB On-chip voltage reference and sample-and-hold circuit ADC 2 V p-p differential analog input VIN+B D0B DNL = 0.45 LSB DCOB Serial port control options Offset binary, gray code, or twos complement data format DIVIDE DUTY CYCLE MODE 1 TO 8 STABILIZER CONTROLS Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider CLK+ CLK SYNC DCS PDWN DFS OEB Data output multiplex option Figure 1. Built-in selectable digital test pattern generation Energy-saving power-down modes PRODUCT HIGHLIGHTS Data clock out with programmable clock and data 1. The AD9251 operates from a single 1.8 V analog power alignment supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent APPLICATIONS performance for input frequencies up to 200 MHz and is Communications designed for low cost, low power, and ease of use. Diversity radio systems 3. A standard serial port interface supports various product Multimode digital receivers features and functions, such as data output formatting, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA internal clock divider, power-down, DCO/DATA timing I/Q demodulation systems and offset adjustments, and voltage reference modes. Smart antenna systems 4. The AD9251 is packaged in a 64-lead RoHS compliant Battery-powered instruments LFCSP that is pin compatible with the AD9268 16-bit Hand held scope meters ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, Portable medical imaging and the AD9204 10-bit ADC, enabling a simple migration Ultrasound path between 10-bit and 16-bit converters sampling from Radar/LIDAR 20 MSPS to 125 MSPS. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com MUX OPTION CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 07938-001AD9251 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 23 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 24 Functional Block Diagram .............................................................. 1 Channel/Chip Synchronization ................................................ 26 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 26 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 27 General Description ......................................................................... 3 Timing.......................................................................................... 27 Specifications ..................................................................................... 4 Built-In Self-Test (BIST) and Output Test .................................. 28 DC Specifications ......................................................................... 4 Built-In Self-Test (BIST) ............................................................ 28 AC Specifications .......................................................................... 5 Output Test Modes ..................................................................... 28 Digital Specifications ................................................................... 6 Serial Port Interface (SPI) .............................................................. 29 Switching Specifications .............................................................. 7 Configuration Using the SPI ..................................................... 29 Timing Specifications .................................................................. 8 Hardware Interface ..................................................................... 30 Absolute Maximum Ratings .......................................................... 10 Configuration Without the SPI ................................................ 30 Thermal Characteristics ............................................................ 10 SPI Accessible Features .............................................................. 30 ESD Caution ................................................................................ 10 Memory Map .................................................................................. 31 Pin Configuration and Function Descriptions ........................... 11 Reading the Memory Map Register Table ............................... 31 Typical Performance Characteristics ........................................... 13 Open Locations .......................................................................... 31 AD9251-80 .................................................................................. 13 Default Values ............................................................................. 31 AD9251-65 .................................................................................. 15 Memory Map Register Table ..................................................... 32 AD9251-40 .................................................................................. 16 Memory Map Register Descriptions ........................................ 34 AD9251-20 .................................................................................. 17 Applications Information .............................................................. 35 Equivalent Circuits ......................................................................... 18 Design Guidelines ...................................................................... 35 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 36 ADC Architecture ...................................................................... 20 Ordering Guide .......................................................................... 36 Analog Input Considerations .................................................... 20 REVISION HISTORY 9/2016Rev. A to Rev. B Changes to Internal Reference Connection Section .................. 23 Changes to Figure 3 .......................................................................... 8 Moved Channel/Chip Synchronization Section ......................... 26 Change to Table 15 ......................................................................... 30 10/2009Rev. 0 to Rev. A Changes to Reading the Memory Map Register Changes to Features .......................................................................... 1 Table Section ................................................................................... 31 Change to Table 1 ............................................................................. 4 Changes to Table 16 ....................................................................... 32 Moved Timing Diagrams................................................................. 8 Deleted Table 11 Renumbered Sequentially .............................. 22 7/2009Revision 0: Initial Version Rev. B Page 2 of 36