14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter Data Sheet AD9245 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD Single 3 V supply operation (2.7 V to 3.6 V) SNR = 72.7 dBc to Nyquist AD9245 SFDR = 83.0 dBc to Nyquist VIN+ 8-STAGE SHA MDAC1 A/D Low power 1 1/2-BIT PIPELINE VIN 366 mW at 80 MSPS 4 16 3 300 mW at 65 MSPS A/D REFT 165 mW at 40 MSPS REFB CORRECTION LOGIC OTR 90 mW at 20 MSPS 14 Differential input with 500 MHz bandwidth OUTPUT BUFFERS On-chip reference and sample-and-hold D13 (MSB) DNL = 0.5 LSB VREF D0 (LSB) Flexible analog input: 1 V p-p to 2 V p-p range SENSE CLOCK Offset binary or twos complement data format 0.5V MODE DUTY CYCLE SELECT Clock duty-cycle stabilizer REF STABILIZER SELECT APPLICATIONS AGND CLK PDWN MODE DGND Medical imaging equipment Figure 1. IF sampling in communications receivers WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA A single-ended clock input is used to control all internal con- Battery-powered instruments version cycles. A duty cycle stabilizer (DCS) compensates for Hand-held scopemeters wide variations in the clock duty cycle while maintaining Spectrum analyzers excellent overall ADC performance. The digital output data is Power-sensitive military applications presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that GENERAL DESCRIPTION can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the The AD9245 is a monolithic, single 3 V supply, 14-bit, AD9245 is available in a 32-lead LFCSP and is specified over 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital the industrial temperature range (40C to +85C). converter (ADC) featuring a high performance sample-and- PRODUCT HIGHLIGHTS hold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error 1. The AD9245 operates from a single 3 V power supply and correction logic to provide 14-bit accuracy and guarantee no features a separate digital output driver supply to missing codes over the full operating temperature range. accommodate 2.5 V and 3.3 V logic families. 2. The patented SHA input maintains excellent performance for The wide bandwidth, truly differential SHA allows a variety of input frequencies up to 100 MHz and can be configured for user-selectable input ranges and common modes, including single-ended or differential operation. single-ended applications. It is suitable for multiplexed systems 3. The AD9245 is pin-compatible with the AD9215, AD9235, that switch full-scale voltage levels in successive channels and and AD9236. This allows a simplified migration from 10 bits for sampling single-channel inputs at frequencies well beyond to 14 bits and 20 MSPS to 80 MSPS. the Nyquist rate. Combined with power and cost savings over 4. The clock DCS maintains overall ADC performance over a previously available analog-to-digital converters, the AD9245 is suitable for applications in communications, imaging, and wide range of clock pulse widths. medical ultrasound. 5. The OTR output bit indicates when the signal is beyond the selected input range. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 03583-001AD9245 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 13 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 18 General Description ......................................................................... 1 Analog Input and Reference Overview ................................... 18 Functional Block Diagram .............................................................. 1 Clock Input Considerations ...................................................... 19 Product Highlights ........................................................................... 1 Jitter Considerations .................................................................. 20 Revision History ............................................................................... 2 Power Dissipation and Standby Mode .................................... 20 Specifications ..................................................................................... 3 Digital Outputs ........................................................................... 20 DC Specifications ......................................................................... 3 Timing.......................................................................................... 21 AC Specifications .......................................................................... 5 Voltage Reference ....................................................................... 21 Digital Specifications ................................................................... 7 Internal Reference Connection ................................................ 21 Switching Specifications .............................................................. 8 External Reference Operation .................................................. 22 Absolute Maximum Ratings ............................................................ 9 Operational Mode Selection ..................................................... 22 Thermal Resistance ...................................................................... 9 Evaluation Board ........................................................................ 22 ESD Caution .................................................................................. 9 Outline Dimensions ....................................................................... 29 Terminology .................................................................................... 10 Ordering Guide .......................................................................... 29 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 12 REVISION HISTORY 5/13Rev. D to Rev. E Changes to Table 5 ............................................................................. 7 Changed CP-32-2 to CP-32-7 ........................................... Universal Changes to Table 6 ............................................................................. 8 Changes to Figure 3 and Table 9 ................................................... 11 Deleted Explanation of Test Levels Table ....................................... 8 Changes to Figure 40 ...................................................................... 19 Added Figure 26 to Figure 31 Renumbered Sequentially ........ 16 Changes to Ordering Guide .......................................................... 29 Added Figure 32 to Figure 37 Renumbered Sequentially ........ 17 Changes to Figure 39 ...................................................................... 18 1/06Rev. C to Rev. D Changes to Clock Input Consideration Section ......................... 19 Changes to Differential Input Configurations Section and Changes to Figure 44 ...................................................................... 20 Figure 40 .......................................................................................... 19 Changes to Table 10 ....................................................................... 21 Changes to Internal Reference Connection Section .................. 21 Changes to Figure 51 ...................................................................... 25 Changes to Figure 49 ...................................................................... 23 Changes to Table 12 ....................................................................... 28 Changes to Figure 50 ...................................................................... 24 Changes to Ordering Guide .......................................................... 29 Updated Outline Dimensions ....................................................... 29 Changes to Table 12 ........................................................................ 28 Updated Outline Dimensions ....................................................... 29 10/03Rev. A to Rev. B Changes to Ordering Guide .......................................................... 29 Changes to Figure 33 ...................................................................... 17 8/05Rev. B to Rev. C 5/03Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Figure 30 ...................................................................... 15 Changes to Features, Applications, General Description, and Changes to Figure 37 ...................................................................... 19 Product Highlights ........................................................................... 1 Changes to Figure 38 ...................................................................... 20 Changes to Figure 39 ...................................................................... 21 Added Table 1 Renumbered Sequentially .................................... 3 Changes to Table 2 ............................................................................ 4 Changes to Table 10 ....................................................................... 24 Added Table 3 Renumbered Sequentially .................................... 5 Changes to the Ordering Guide ................................................... 25 Changes to Table 4 ............................................................................ 6 Rev. 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