Complete 12-Bit, 65 MSPS a ADC Converter AD9226 FEATURES FUNCTIONAL BLOCK DIAGRAM Signal-to-Noise Ratio: 69 dB f = 31 MHz IN DRVDD CLK AVDD Spurious-Free Dynamic Range: 85 dB f = 31 MHz IN Intermodulation Distortion of 75 dBFS f = 140 MHz IN DUTY CYCLE STABILIZER ENOB = 11.1 f = 10 MHz IN SHA Low-Power Dissipation: 475 mW VINA 8-STAGE MDAC1 A/D 1-1/2-BIT PIPELINE No Missing Codes Guaranteed VINB 4 Differential Nonlinearity Error: 0.6 LSB A/D 3 16 Integral Nonlinearity Error: 0.6 LSB CAPT CALIBRATION ROM Clock Duty Cycle Stabilizer CORRECTION LOGIC CAPB 12 Patented On-Chip Sample-and-Hold with VREF OTR OUTPUT BUFFERS Full Power Bandwidth of 750 MHz BIT 1 SENSE Straight Binary or Twos Complement Output Data (MSB) 1V REF MODE BIT 12 28-Lead SSOP, 48-Lead LQFP SELECT SELECT AD9226 (LSB) Single 5 V Analog Supply, 3 V/5 V Driver Supply REFCOM MODE AVSS DRVSS Pin-Compatible to AD9220, AD9221, AD9223, AD9224, AD9225 PRODUCT DESCRIPTION The AD9226 has two important mode functions. One will set The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS the data format to binary or twos complement. The second will analog-to-digital converter with an on-chip, high-performance make the ADC immune to clock duty cycle variations. sample-and-hold amplifier and voltage reference. The AD9226 uses a multistage differential pipelined architecture with a pat- PRODUCT HIGHLIGHTS ented input stage and output error correction logic to provide IF SamplingThe patented SHA input can be configured for 12-bit accuracy at 65 MSPS data rates. There are no missing either single-ended or differential inputs. It will maintain out- codes over the full operating temperature range (guaranteed). standing AC performance up to input frequencies of 300 MHz. The input of the AD9226 allows for easy interfacing to both Low PowerThe AD9226 at 475 mW consumes a fraction of imaging and communications systems. With a truly differential the power presently available in existing, high-speed monolithic input structure, the user can select a variety of input ranges and solutions. offsets including single-ended applications. Out of Range (OTR)The OTR output bit indicates when The sample-and-hold amplifier (SHA) is well suited for IF the input signal is beyond the AD9226s input range. undersampling schemes such as in single-channel communi- Single SupplyThe AD9226 uses a single 5 V power supply cation applications with input frequencies up to and well simplifying system power supply design. It also features a sepa- beyond Nyquist frequencies. rate digital output driver supply line to accommodate 3 V and The AD9226 has an on-board programmable reference. For sys- 5 V logic families. tem design flexibility, an external reference can also be chosen. Pin CompatibilityThe AD9226 is similar to the AD9220, A single clock input is used to control all internal conversion AD9221, AD9223, AD9224, and AD9225 ADCs. cycles. An out-of-range signal indicates an overflow condition Clock Duty Cycle StabilizerMakes conversion immune to that can be used with the most significant bit to determine low varying clock pulsewidths. or high overflow. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD9226SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, f = 65 MSPS, VREF = 2.0 V, Differential inputs, T to T unless otherwise SAMPLE MIN MAX DC SPECIFICATIONS noted.) Parameter Temp Test Level Min Typ Max Unit RESOLUTION 12 Bits ACCURACY Integral Nonlinearity (INL) Full V 0.6 LSB 25CI 1.6 LSB Differential Nonlinearity (DNL) Full V 0.6 LSB 25CI 1.0 LSB No Missing Codes Guaranteed Full I 12 Bits Zero Error Full V 0.3 % FSR 25CI 1.4 % FSR Gain Error 25CI 2.0 % FSR Full V 0.6 % FSR TEMPERATURE DRIFT Zero Error Full V 2 ppm/C 1 Gain Error Full V 26 ppm/C 2 Gain Error Full V 0.4 ppm/C POWER SUPPLY REJECTION AVDD (5 V 0.25 V) Full V 0.05 % FSR 25CI 0.4 % FSR INPUT REFERRED NOISE VREF = 1.0 V Full V 0.5 LSB rms VREF = 2.0 V Full V 0.25 LSB rms ANALOG INPUT Input Span (VREF = 1 V) Full V 1 V p-p (VREF = 2 V) Full V 2 V p-p Input (VINA or VINB) Range Full IV 0 AVDD V Input Capacitance Full V 7 pF INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full V 1.0 V Output Voltage Tolerance (1 V Mode) 25CI 15 mV Output Voltage (2.0 V Mode) Full V 2.0 V Output Voltage Tolerance (2.0 V Mode) 25CI 29 mV Output Current (Available for External Loads) Full V 1.0 mA 3 Load Regulation Full V 0.7 mV 25C I 1.5 mV REFERENCE INPUT RESISTANCE Full V 5 k POWER SUPPLIES Supply Voltages AVDD Full V 4.75 5 5.25 V (5% AVDD Operating) DRVDD Full V 2.85 5.25 V (5% DRVDD Operating) Supply Current 4 IAVDD Full V 86 mA (2 V External VREF) 25C I 90.5 mA (2 V External VREF) 5 IDRVDD Full V 14.6 mA (2 V External VREF) 25C I 16.5 mA (2 V External VREF) 4, 5 POWER CONSUMPTION Full V 475 25C I 500 mW (2 V External VREF) NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9226). 4 AVDD = 5 V 5 DRVDD = 3 V Specifications subject to change without notice. 2 REV. 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