Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface AD7866 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 12-Bit, 2-Channel ADC V DAAV DV REF CAP DD DD REF SELECT Fast Throughput Rate: 1 MSPS Specified for V of 2.7 V to 5.25 V DD Low Power 2.5V BUF AD7866 REF 11.4 mW Max at 1 MSPS with 3 V Supplies 12-BIT 24 mW Max at 1 MSPS with 5 V Supplies V A1 OUTPUT SUCCESSIVE D A T/H OUT MUX DRIVERS Wide Input Bandwidth V APPROXIMATION A2 ADC 70 dB SNR at 300 kHz Input Frequency On-Board Reference 2.5 V A0 RANGE 40 C to +125 C Operation CONTROL SCLK LOGIC Flexible Power/Throughput Rate Management CS Simultaneous Conversion/Read V DRIVE No Pipeline Delays 12-BIT TM TM V B1 High Speed Serial Interface SPI /QSPI / OUTPUT SUCCESSIVE D B MUX T/H OUT TM DRIVERS V APPROXIMATION B2 MICROWIRE /DSP Compatible ADC Shutdown Mode: 1 A Max 20-Lead TSSOP Package BUF AGND AGND D B DGND GENERAL DESCRIPTION CAP The AD7866 is a dual 12-bit high speed, low power, successive approximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 1 MSPS. The device contains two ADCs, each preceded by a low noise, PRODUCT HIGHLIGHTS wide bandwidth track-and-hold amplifier that can handle 1. The AD7866 features two complete ADC functions, allowing input frequencies in excess of 10 MHz. simultaneous sampling and conversion of two channels. Each ADC has a 2-channel input multiplexer. The conversion result The conversion process and data acquisition are controlled of both channels is available simultaneously on separate data using standard control inputs, allowing easy interfacing to lines, or may be taken on one data line if only one serial port microprocessors or DSPs. The input signal is sampled on the is available. falling edge of CS conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. 2. High Throughput with Low Power ConsumptionThe There are no pipelined delays associated with the part. AD7866 offers a 1 MSPS throughput rate with 11.4 mW maximum power consumption when operating at 3 V. The AD7866 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 3 V 3. Flexible Power/Throughput Rate ManagementThe conver- supplies and 1 MSPS throughput rate, the part consumes a sion rate is determined by the serial clock, allowing the power maximum of 3.8 mA. With 5 V supplies and 1 MSPS, the consumption to be reduced as the conversion time is reduced current consumption is a maximum of 4.8 mA. The part also through a SCLK frequency increase. Power efficiency can be offers flexible power/throughput rate management when maximized at lower throughput rates if the part enters sleep operating in sleep mode. during conversions. The analog input range for the part can be selected to be a 0 V 4. No Pipeline DelayThe part features two standard successive to V range or a 2 V range with either straight binary or approximation ADCs with accurate control of the sampling REF REF twos complement output coding. The AD7866 has an on-chip instant via a CS input and once off conversion control. 2.5 V reference that can be overdriven if an external reference is preferred. Each on-board ADC can also be supplied with a separate individual external reference. The AD7866 is available in a 20-lead thin shrink small outline (TSSOP) package. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies.(T = T to T , V = 2.7 V to 5.25 V, V = 2.7 V to 5.25 V, Reference = 2.5 V A MIN MAX DD DRIVE AD7866SPECIFICATIONS External on D A and D B, f = 20 MHz, unless otherwise noted.) CAP CAP SCLK 1 1 Parameter A Version B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE 2 Signal to Noise + Distortion (SINAD) 68 68 dB min f = 300 kHz Sine Wave, f = 1 MSPS IN S 2 Total Harmonic Distortion (THD) 75 75 dB max f = 300 kHz Sine Wave, f = 1 MSPS IN S 2 Peak Harmonic or Spurious Noise (SFDR) 76 76 dB max f = 300 kHz Sine Wave, f = 1 MSPS IN S 2 Intermodulation Distortion (IMD) Second Order Terms 88 88 dB typ Third Order Terms 88 88 dB typ Channel-to-Channel Isolation 88 88 dB typ SAMPLE AND HOLD 3 Aperture Delay 10 10 ns max 3 Aperture Jitter 50 50 ps typ 3 Aperture Delay Matching 200 200 ps max Full Power Bandwidth 12 12 MHz typ 3 dB 22 MHz typ 0.1 dB DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity 1.5 1 LSB max B Grade, 0 V to V Range Only 0.5 LSB typ REF 1.5 LSB max 0 V to 2 V Range 0.5 LSB typ REF Differential Nonlinearity 0.95/+1.25 0.95/+1.25 LSB max Guaranteed No Missed Codes to 12 Bits 0 V to V Input Range Straight Binary Output Coding REF Offset Error 8 8 LSB max Offset Error Match 1.2 1.2 LSB typ Gain Error 2.5 2.5 LSB max Gain Error Match 0.2 0.2 LSB typ 2 V Input Range V to +V Biased about V with REF REF REF REF Positive Gain Error 2.5 2.5 LSB max Twos Complement Output Coding Zero Code Error 8 8 LSB max Zero Code Error Match 0.2 0.2 LSB typ Negative Gain Error 2.5 2.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V RANGE Pin Low upon CS Falling Edge REF REF 0 to 2 V 0 to 2 V V RANGE Pin High upon CS Falling Edge REF REF DC Leakage Current 500 500 nA max T = 40 C to +85 C A 11 A max 85 C < T 125 C A Input Capacitance 30 30 pF typ When in Track 10 10 pF typ When in Hold REFERENCE INPUT/OUTPUT Reference Input Voltage 2.5 2.5 V 1% for Specified Performance 4 Reference Input Voltage Range 2/3 2/3 V min/V max REF SELECT Pin Tied High DC Leakage Current 30 30 A max V Pin REF 160 160 A max D A, D B Pins CAP CAP Input Capacitance 20 20 pF typ 5 Reference Output Voltage 2.45/2.55 2.45/2.55 V min/V max 6 V Output Impedance 25 25 typ V = 5 V REF DD 45 45 typ V = 3 V DD Reference Temperature Coefficient 50 50 ppm/C typ REF OUT Error (T to T ) 15 15 mV typ MIN MAX LOGIC INPUTS Input High Voltage, V 0.7 V 0.7 V V min INH DRIVE DRIVE Input Low Voltage, V 0.3 V 0.3 V V max INL DRIVE DRIVE Input Current, I 1 1 A max Typically 15 nA, V = 0 V or V IN IN DRIVE 3 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V V 0.2 V 0.2 V min I = 200 A OH DRIVE DRIVE SOURCE Output Low Voltage, V 0.4 0.4 V max I = 200 A OL SINK Floating-State Leakage Current 1 1 A max V = 2.7 V to 5.25 V DD 3 Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary Selectable with Either Input Range Twos Complement 2 REV. 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