3 V/5 V, CMOS, 500 mA a Signal Conditioning ADC AD7714 FEATURES FUNCTIONAL BLOCK DIAGRAM Charge Balancing ADC DV AV REF IN() REF IN(+) DD DD 24 Bits No Missing Codes 0.0015% Nonlinearity AV DD CHARGE Five-Channel Programmable Gain Front End BALANCING 1mA A/D CONVERTER Gains from 1 to 128 STANDBY S -D AIN1 Can Be Configured as Three Fully Differential MODULATOR AIN2 SYNC AIN3 Inputs or Five Pseudo-Differential Inputs BUFFER PGA DIGITAL FILTER AIN4 Three-Wire Serial Interface AIN5 A = 1128 AIN6 SPI, QSPI, MICROWIRE and DSP Compatible 1mA 3 V (AD7714-3) or 5 V (AD7714-5) Operation SERIAL INTERFACE REGISTER BANK SCLK Low Noise (<150 nV rms) AGND Low Current (350 mA typ) with Power-Down (5 mA typ) BUFFER CS AD7714Y Grade: MCLK IN DIN CLOCK MCLK OUT GENERATION +2.7 V to 3.3 V or +4.75 V to +5.25 V Operation DOUT 0.0010% Linearity Error AD7714 408C to +1058C Temperature Range Schmitt Trigger on SCLK and DIN DGND POL RESET AGND DRDY Low Current (226 mA typ) with Power-Down (4 mA typ) for three-wire operation. Gain settings, signal polarity and channel Lower Power Dissipation than Standard AD7714 selection can be configured in software using the serial port. The Available in 24-Lead TSSOP Package AD7714 provides self-calibration, system calibration and back- Low-Pass Filter with Programmable Filter Cutoffs ground calibration options and also allows the user to read and Ability to Read/Write Calibration Coefficients write the on-chip calibration registers. APPLICATIONS CMOS construction ensures very low power dissipation, and the Portable Industrial Instruments power-down mode reduces the standby power consumption to Portable Weigh Scales 15 m W typ. The part is available in a 24-pin, 0.3 inch-wide, plastic Loop-Powered Systems dual-in-line package (DIP) a 24-lead small outline (SOIC) Pressure Transducers package, a 28-lead shrink small outline package (SSOP) and a 24-lead thin shrink small outline package (TSSOP). GENERAL DESCRIPTION The AD7714 is a complete analog front end for low-frequency PRODUCT HIGHLIGHTS measurement applications. The device accepts low level signals 1. The AD7714Y offers the following features in addition to the directly from a transducer and outputs a serial digital word. It standard AD7714: wider temperature range, Schmitt trigger employs a sigma-delta conversion technique to realize up to 24 on SCLK and DIN, operation down to 2.7 V, lower power bits of no missing codes performance. The input signal is applied consumption, better linearity, and availability in 24-lead to a proprietary programmable gain front end based around an TSSOP package. analog modulator. The modulator output is processed by an on- 2. The AD7714 consumes less than 500 m A (f = 1 MHz) CLK IN chip digital filter. The first notch of this digital filter can be or 1 mA (f = 2.5 MHz) in total supply current, making CLK IN programmed via the on-chip control register allowing adjust- it ideal for use in loop-powered systems. ment of the filter cutoff and settling time. 3. The programmable gain channels allow the AD7714 to ac- The part features three differential analog inputs (which can also cept input signals directly from a strain gage or transducer be configured as five pseudo-differential analog inputs) as well as a removing a considerable amount of signal conditioning. differential reference input. It operates from a single supply (+3 V 4. The AD7714 is ideal for microcontroller or DSP processor or +5 V). The AD7714 thus performs all signal conditioning and applications with a three-wire serial interface reducing the num- conversion for a system consisting of up to five channels. ber of interconnect lines and reducing the number of opto- The AD7714 is ideal for use in smart, microcontroller- or DSP- couplers required in isolated systems. The part contains based systems. It features a serial interface that can be configured on-chip registers that allow control over filter cutoff, input gain, channel selection, signal polarity and calibration modes. See page 39 for data sheet index. 5. The part features excellent static performance specifications SPI and QSPI are trademarks of Motorola, Inc. with 24-bit no missing codes, 0.0015% accuracy and low MICROWIRE is a trademark of National Semiconductor Corporation. rms noise (140 nV). Endpoint errors and the effects of tem- REV. C perature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (AV = +5 V, DV = +3.3 V or +5 V, REF IN(+) = +2.5 V REF IN() = AGND AD7714-5SPECIFICATIONS DD DD f = 2.4576 MHz unless otherwise noted. All specifications T to T unless otherwise noted.) CLK IN MIN MAX 1 Parameter A Versions Units Conditions/Comments STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. Bipolar Mode. For Filter Notches 60 Hz 22 Bits min For Filter Notch = 100 Hz 18 Bits min For Filter Notch = 250 Hz 15 Bits min For Filter Notch = 500 Hz 12 Bits min For Filter Notch = 1 kHz Output Noise See Tables I to IV Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity 0.0015 % of FSR max Filter Notches 60 Hz Unipolar Offset Error See Note 2 3 Unipolar Offset Drift 0.5 m V/ C typ For Gains of 1, 2, 4 0.3 m V/ C typ For Gains of 8, 16, 32, 64, 128 Bipolar Zero Error See Note 2 3 Bipolar Zero Drift 0.5 m V/ C typ For Gains of 1, 2, 4 0.3 m V/ C typ For Gains of 8, 16, 32, 64, 128 4 Positive Full-Scale Error See Note 2 3, 5 Full-Scale Drift 0.5 m V/ C typ For Gains of 1, 2, 4 0.3 m V/ C typ For Gains of 8, 16, 32, 64, 128 6 Gain Error See Note 2 3, 7 Gain Drift 0.5 ppm of FSR/ C typ Bipolar Negative Full-Scale Error 0.0015 % of FSR max Typically 0.0004% 3 Bipolar Negative Full-Scale Drift 1 m V/ C typ For Gains of 1, 2, 4 0.6 m V/ C typ For Gains of 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted Input Common-Mode Rejection (CMR) 90 dB min At DC. Typically 102 dB 8 Normal-Mode 50 Hz Rejection 100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, 0.02 f NOTCH 8 Normal-Mode 60 Hz Rejection 100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, 0.02 f NOTCH 8 Common-Mode 50 Hz Rejection 150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, 0.02 f NOTCH 8 Common-Mode 60 Hz Rejection 150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, 0.02 f NOTCH 9 Common-Mode Voltage Range AGND to AV V min to V max AIN for BUFFER = 0 and REF IN DD 9 Absolute AIN/REF IN Voltage AGND 30 mV V min AIN for BUFFER = 0 and REF IN AV + 30 mV V max DD 9 Absolute/Common-Mode AIN Voltage AGND + 50 mV V min BUFFER = 1. A Version AV 1.5 V V max DD 8 AIN Input Current 1 nA max A Version 8 AIN Sampling Capacitance 7 pF max 10 11 AIN Differential Voltage Range 0 to +V /GAIN nom Unipolar Input Range (B/U Bit of Filter High Register = 1) REF V /GAIN nom Bipolar Input Range (B/U Bit of Filter High Register = 0) REF AIN Input Sampling Rate, f GAIN f /64 For Gains of 1, 2, 4 S CLK IN f /8 For Gains of 8, 16, 32, 64, 128 CLK IN REF IN(+) REF IN() Voltage +2.5 V nom 1% for Specified Performance. Functional with Lower V REF REF IN Input Sampling Rate, f f /64 S CLK IN LOGIC INPUTS Input Current 10 m A max All Inputs Except MCLK IN V , Input Low Voltage 0.8 V max DV = +5 V INL DD V , Input Low Voltage 0.4 V max DV = +3.3 V INL DD V , Input High Voltage 2.4 V min DV = +5 V INH DD V , Input High Voltage 2.0 V min DV = +3.3 V INH DD MCLK IN Only V , Input Low Voltage 0.8 V max DV = +5 V INL DD V , Input Low Voltage 0.4 V max DV = +3.3 V INL DD V , Input High Voltage 3.5 V min DV = +5 V INH DD V , Input High Voltage 2.5 V min DV = +3.3 V INH DD LOGIC OUTPUTS (Including MCLK OUT) 12 V , Output Low Voltage 0.4 V max I = 800 m A Except for MCLK OUT. DV = +5 V OL SINK DD 12 V , Output Low Voltage 0.4 V max I = 100 m A Except for MCLK OUT. DV = +3.3 V OL SINK DD 12 V , Output High Voltage 4.0 V min I = 200 m A Except for MCLK OUT. DV = +5 V OH SOURCE DD 12 V , Output High Voltage DV 0.6 V V min I = 100 m A Except for MCLK OUT. DV = +3.3 V OH DD SOURCE DD Floating State Leakage Current 10 m A max 13 Floating State Output Capacitance 9 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode NOTES 1 Temperature range is as follows: A Versions: 40 C to +85 C. 2 A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest. 3 Recalibration at any temperature will remove these drift errors. 4 Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. 5 Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 6 Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale ErrorUnipolar Offset Error for unipolar ranges and Full-Scale ErrorBipolar Zero Error for bipolar ranges. 2 REV. C