a Signal Conditioning ADC AD7710 FUNCTIONAL BLOCK DIAGRAM FEATURES Charge Balancing ADC REF REF 24 Bits, No Missing Codes AV DV IN () IN (+) V REF OUT DD DD BIAS 0.0015% Nonlinearity AV DD 2-Channel Programmable Gain Front End 2.5V REFERENCE Gains from 1 to 128 4.5 A Differential Inputs CHARGE-BALANCING A/D CONVERTER Low-Pass Filter with Programmable Filter Cutoffs AIN1(+) Ability to Read/Write Calibration Coefficients AUTO-ZEROED SYNC AIN1() M PGA DIGITAL - FILTER Bidirectional Microcontroller Serial Interface U MODULATOR AIN2(+) X Internal/External Reference Option A = 1 128 AIN2() Single- or Dual-Supply Operation MCLK AV CLOCK IN Low Power (25 mW Typ) with Power-Down Mode DD GENERATION MCLK (7 mW Typ) OUT 20 A SERIAL INTERFACE APPLICATIONS CONTROL OUTPUT Weigh Scales I REGISTER OUT REGISTER Thermocouples AD7710 Process Control Smart Transmitters Chromatography AGND DGND RFS TFS MODE SDATA SCLK DRDY A0 V SS GENERAL DESCRIPTION The AD7710 is a complete analog front end for low frequency CMOS construction ensures low power dissipation, and a soft- measurement applications. The device accepts low level signals ware programmable power-down mode reduces the standby directly from a strain gage or transducer and outputs a serial power consumption to only 7 mW typical. The part is available digital word. It employs a sigma-delta conversion technique to in a 24-lead, 0.3 inch-wide, plastic and hermetic dual-in-line realize up to 24 bits of no missing codes performance. The input package (DIP) as well as a 24-lead small outline (SOIC) package. signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is PRODUCT HIGHLIGHTS processed by an on-chip digital filter. The first notch of this 1. The programmable gain front end allows the AD7710 to digital filter can be programmed via the on-chip control register, accept input signals directly from a strain gage or transducer, allowing adjustment of the filter cutoff and settling time. removing a considerable amount of signal conditioning. The part features two differential analog inputs and a differen- 2. The AD7710 is ideal for microcontroller or DSP processor tial reference input. Typically, one of the channels will be used applications with an on-chip control register that allows as the main channel with the second channel used as an auxil- control over filter cutoff, input gain, channel selection, signal iary input to measure a second voltage periodically. It can be polarity, and calibration modes. operated from a single supply (by tying the V pin to AGND), SS 3. The AD7710 allows the user to read and write the on-chip provided that the input signals on the analog inputs are more calibration registers. This means that the microcontroller has positive than 30 mV. By taking the V pin negative, the part SS much greater control over the calibration procedure. can convert signals down to V on its inputs. The AD7710 REF thus performs all signal conditioning and conversion for a single- 4. No missing codes ensures true, usable, 23-bit dynamic range or dual-channel system. coupled with excellent 0.0015% accuracy. The effects of temperature drift are eliminated by on-chip self-calibration, The AD7710 is ideal for use in smart, microcontroller based which removes zero-scale and full-scale errors. systems. Input channel selection, gain settings, and signal polar- ity can be configured in software using the bidirectional serial port. The AD7710 contains self-calibration, system calibration, and background calibration options, and also allows the user to read and write the on-chip calibration registers. REV. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781/326-8703 2004 Analog Devices, Inc. All rights reserved.(AV = +5 V 5% DV = +5 V 5% V = 0 V or 5 V 5% REF IN(+) = +2.5 V AD7710SPECIFICATIONS DD DD SS REF IN() = AGND MCLK IN = 10 MHz unless otherwise noted. All specifications T to T , unless otherwise noted.) MIN MAX 1 Parameter A, S Versions Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches 60 Hz 22 Bits min For Filter Notch = 100 Hz 18 Bits min For Filter Notch = 250 Hz 15 Bits min For Filter Notch = 500 Hz 12 Bits min For Filter Notch = 1 kHz Output Noise Tables I and II Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity +25C 0.0015 % of FSR max Filter Notches 60 Hz T to T 0.003 % of FSR max Typically 0.0003% MIN MAX 2, 3 Positive Full-Scale Error See Note 4 Excluding Reference 5 Full-Scale Drift 1 V/C typ Excluding Reference. For Gains of 1, 2 0.3 V/C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 2 Unipolar Offset Error See Note 4 5 Unipolar Offset Drift 0.5 V/C typ For Gains of 1, 2 0.25 V/C typ For Gains of 4, 8, 16, 32, 64, 128 2 Bipolar Zero Error See Note 4 5 Bipolar Zero Drift 0.5 V/C typ For Gains of 1, 2 0.25 V/C typ For Gains of 4, 8, 16, 32, 64, 128 Gain Drift 2 ppm/C typ 2 Bipolar Negative Full-Scale Error 25C 0.003 % of FSR max Excluding Reference T to T 0.006 % of FSR max Typically 0.0006% MIN MAX 5 Bipolar Negative Full-Scale Drift 1 V/C typ Excluding Reference. For Gains of 1, 2 0.3 V/C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Input Common-Mode Rejection (CMR) 100 dB min At DC and AV = 5 V DD 90 dB min At DC and AV = 10 V DD 6 Common-Mode Voltage Range V to AV V min to V max SS DD 7 Normal-Mode 50 Hz Rejection 100 dB min For Filter Notches of 10, 25, 50 Hz, 0.02 f NOTCH 7 Normal-Mode 60 Hz Rejection 100 dB min For Filter Notches of 10, 30, 60 Hz, 0.02 f NOTCH 7 Common-Mode 50 Hz Rejection 150 dB min For Filter Notches of 10, 25, 50 Hz, 0.02 f NOTCH 7 Common-Mode 60 Hz Rejection 150 dB min For Filter Notches of 10, 30, 60 Hz, 0.02 f NOTCH 7 DC Input Leakage Current 25C10 pA max T to T 1 nA max MIN MAX 7 Sampling Capacitance 20 pF max 8 Analog Inputs 9 Input Voltage Range For Normal Operation. Depends on Gain Selected 10 0 to +V nom Unipolar Input Range (B/U Bit of Control Register = 1) REF V nom Bipolar Input Range (B/U Bit of Control Register = 0) REF Input Sampling Rate, f See Table III S Reference Inputs 11 REF IN(+) REF IN() Voltage 2.5 to 5 V min to V max For Specified Performance. Part Is Functional with Lower V Voltages REF Input Sampling Rate, f f /256 S CLK IN NOTES 1 Temperature ranges are as follows: A Version, 40C to +85C S Version, 55C to +125C. See also Note 16. 2 Applies after calibration at the temperature of interest. 3 Positive full-scale error applies to both unipolar and bipolar input ranges. 4 These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 V typical after self-calibration or background calibration. 5 Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN() does not exceed AV + 30 mV and V 30 mV. DD SS 7 These numbers are guaranteed by design and/or characterization. 8 The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resistance depends on the selected gain (see Tables IV and V). 9 The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1() and AIN2() inputs. The absolute voltage on the analog inputs should not go more positive than AV + 30 mV or go more negative than V 30 mV. DD SS 10 V = REF IN(+) REF IN(). REF 11 The reference input voltage range may be restricted by the input voltage range requirement on the V input. BIAS 2 REV. G