10-Bit Monitor and Control System with ADC, DACs, Temperature Sensor, and GPIOs Data Sheet AD7292 FEATURES FUNCTIONAL BLOCK DIAGRAM REF REF DV AV V OUT IN DD DD DRIVE 10-bit SAR ADC 8 multiplexed analog input channels TEMPERATURE 4 Single-ended mode of operation SENSOR AD7292 Differential mode of operation 1.25V BUF BUF REF 5 V analog input range VIN0 10-BIT V , 2 V , or 4 V input ranges REF REF REF VOUT0 VIN1 DAC Input measured with respect to A or V GND DD VIN2 4 monotonic, 10-bit, 5 V DACs 10-BIT VIN3 CONTROL 10-BIT VOUT1 MUX T/H SAR ADC DAC LOGIC 2 s settling time VIN4 Power-on reset to 0 V VIN5 10-BIT VOUT2 DAC 10 mA sink and source capability VIN6 Internal temperature sensor VIN7 10-BIT 1C accuracy VOUT3 DAC ALERT AND LIMIT 12 general-purpose digital I/O pins REGISTERS Internal 1.25 V reference Built-in monitoring features SPI DIGITAL I/Os INTERFACE Minimum and maximum value register for each channel Programmable alert thresholds Programmable hysteresis SPI interface Temperature range: 40C to +125C Package type: 36-lead LFCSP APPLICATIONS Base station power amplifier (PA) monitoring and control RF control loops Figure 1. Optical communication system control General-purpose system monitoring and control GENERAL DESCRIPTION The AD7292 contains all the functionality required for general- Four 10-bit digital-to-analog converters (DACs) provide outputs purpose monitoring of analog signals and control of external from 0 V to 5 V. An internal, high accuracy, 1.25 V reference devices, integrated into a single-chip solution. The AD7292 provides a separately buffered reference source for both the ADC features an 8-channel, 10-bit SAR ADC, four 10-bit DACs, a and the DACs. 1C accurate internal temperature sensor, and 12 GPIOs to A high accuracy band gap temperature sensor is monitored and aid system monitoring and control. digitized by the 10-bit ADC to give a resolution of 0.03125C. The 10-bit, high speed, low power successive approximation The AD7292 also features built-in limit and alarm functions. register (SAR) ADC is designed to monitor a variety of single- The AD7292 is a highly integrated solution offered in a 36-lead ended input signals. Differential operation is also available by LFCSP package with an operating temperature range of 40C configuring VIN0 and VIN1 to operate as a differential pair. to +125C. The AD7292 offers a register programmable ADC sequencer, which enables the selection of a programmable sequence of channels for conversion. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com GPIO0/ALERT0 GPIO1/ALERT1 GPIO2/DAC DISABLE0 GPIO3/LDAC GPIO4/DAC DISABLE1 GPIO5 GPIO6/BUSY GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 DIN SCLK DOUT CS A GND D GND 10660-001AD7292 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Sequence Register (Address 0x03) ................................. 21 Applications ....................................................................................... 1 Configuration Register Bank (Address 0x05) .......................... 21 Functional Block Diagram .............................................................. 1 Alert Limits Register Bank (Address 0x06) ............................ 30 General Description ......................................................................... 1 Alert Flags Register Bank (Address 0x07) .............................. 31 Revision History ............................................................................... 2 Minimum and Maximum Register Bank (Address 0x08) .... 32 Specifications ..................................................................................... 3 Offset Register Bank (Address 0x09) ....................................... 32 ADC Specifications ...................................................................... 3 DAC Buffer Enable Register (Address 0x0A) ......................... 33 DAC Specifications....................................................................... 4 GPIO Register (Address 0x0B) ................................................. 33 General Specifications ................................................................. 5 Conversion Command Register (Address 0x0E) ................... 34 Temperature Sensor Specifications ............................................ 5 ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) ............................................... 34 Timing Specifications .................................................................. 6 TSENSE Conversion Result Register (Address 0x20) ................ 34 Absolute Maximum Ratings ............................................................ 7 DAC Channel Registers (Address 0x30 to Address 0x33) .... 34 Thermal Resistance ...................................................................... 7 ADC Conversion Control ............................................................. 35 ESD Caution .................................................................................. 7 ADC Conversion Command .................................................... 35 Pin Configuration and Function Descriptions ............................. 8 ADC Sequencer .......................................................................... 36 Typical Performance Characteristics ........................................... 10 DAC Output Control ..................................................................... 37 Theory of Operation ...................................................................... 15 LDAC Operation ........................................................................ 37 Analog Inputs .............................................................................. 15 Simultaneous Update of All DAC Outputs ............................. 37 ADC Transfer Functions ........................................................... 16 Alerts and Limits ............................................................................ 38 Temperature Sensor ................................................................... 17 Alert Limit Monitoring Features .............................................. 38 DAC Operation ........................................................................... 17 Hardware Alert Pins................................................................... 38 Digital I/O Pins ........................................................................... 17 Alert Flag Bits in the Conversion Result Registers ................ 38 Serial Port Interface (SPI) .............................................................. 18 Alert Flags Register Bank .......................................................... 39 Interface Protocol ....................................................................... 18 Minimum and Maximum Conversion Results ...................... 39 Register Structure ........................................................................... 20 Outline Dimensions ....................................................................... 40 Register Descriptions ..................................................................... 21 Ordering Guide .......................................................................... 40 Vendor ID Register (Address 0x00) ......................................... 21 ADC Data Register (Address 0x01) ......................................... 21 REVISION HISTORY 9/14Rev. 0 to Rev. A Changes to VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Section, Changes to Figure 2 .......................................................................... 6 Table 25, and Table 26 .................................................................... 27 Changed t from 4 ns max to 4 ns min and Removed 11 Changes to Figure 40 and Figure 41 ............................................ 35 Endnote 4 Table 5 .......................................................................... 21 Changes to Figure 42 ...................................................................... 36 Changes to Figure 35 ...................................................................... 18 Changes to Table 15 ........................................................................ 21 10/12Revision 0: Initial Version Changes to VIN Filter Subregister (Address 0x13) Section, Conversion Delay Control Subregister (Address 0x14) Section, Table 23, and Table 24 .................................................................... 26 Rev. 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