Data Sheet AD4630-24 24-Bit, 2 MSPS, Dual Channel SAR ADC FEATURES FUNCTIONAL BLOCK DIAGRAM High performance Throughput: 2 MSPS per channel maximum INL: 0.9 ppm maximum from 40C to +125C SNR: 105.7 dB typical THD: 127 dB typical NSD: 166 dBFS/Hz typical Low power 15 mW per channel at 2 MSPS 1.5 mW per channel at 10 kSPS Easy Drive features reduce system complexity Very low 0.6 A input current for dc inputs Figure 1. Wide input common-mode range: (1/128) V to REF +(129/128) V REF GENERAL DESCRIPTION Flexible external reference voltage range: 4.096 V to 5 V Accurate integrated reference buffer with 2 F bypass The AD4630-24 is a two-channel, simultaneous sampling, Easy capacitor Drive, 2 MSPS successive approximation register (SAR) analog-to- 16 digital converter (ADC). With a guaranteed maximum 0.9 ppm Programmable block averaging filter with up to 2 decimation INL and no missing codes at 24 bits, the AD4630-24 achieves Extended sample resolution to 30 bits unparalleled precision from 40C to +125C. Figure 1 shows the Overrange and synchronization bits functional architecture of the AD4630-24. Flexi-SPI digital interface A low drift, internal precision reference buffer eases voltage 1, 2, or 4 SDO lanes per channel allows slower SCK reference sharing with other system circuitry. The AD4630-24 offers Echo clock mode simplifies use of digital isolator a typical dynamic range of 106 dB when using a 5 V reference. Compatible with 1.2 V to 1.8 V logic The low noise floor enables signal chains requiring less gain and 7 mm 7 mm 64-Ball CSP BGA package with internal supply lower power. A block averaging filter with programmable decima- and reference capacitors to help reduce system footprint tion ratio can increase dynamic range up to 153 dB. The wide differential input and common-mode ranges allow inputs to use APPLICATIONS the full V range without saturating, simplifying signal condition- REF ing requirements and system calibration. The improved settling of Automatic test equipment the Easy Drive analog inputs broadens the selection of analog Digital control loops front-end components compatible with the AD4630-24. Both single- Medical instrumentation ended and differential signals are supported. Seismology The versatile Flexi-SPI serial peripheral interface (SPI) eases host Semiconductor manufacturing processor and ADC integration. A wide data clocking window, multi- Scientific instrumentation ple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS. Echo clock mode and ADC master clock mode relax the timing requirements and simplify the use of digital isolators. The 64-ball chip scale package ball grid array (CSP BGA) of the AD4630-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet AD4630-24 TABLE OF CONTENTS Features................................................................ 1 Power Supplies................................................ 25 Applications........................................................... 1 Serial Interface.................................................... 26 Functional Block Diagram......................................1 SPI Signals.......................................................26 General Description...............................................1 Sample Conversion Timing and Data Specifications........................................................ 3 Transfer.......................................................... 28 Timing Specifications......................................... 5 Clocking Modes ...............................................29 Absolute Maximum Ratings................................. 11 Data Clocking Requirements and Timing.........32 Thermal Resistance..........................................11 Layout Guidelines................................................36 Electrostatic Discharge (ESD) Ratings.............11 Registers............................................................. 37 ESD Caution.....................................................11 Register Details................................................... 38 Pin Configuration and Function Descriptions...... 12 Interface Configuration A Register................... 38 Typical Performance Characteristics...................14 Interface Configuration B Register................... 38 Terminology......................................................... 18 Device Configuration Register..........................39 Integral Nonlinearity Error (INL)....................... 18 Chip Type Register...........................................39 Differential Nonlinearity Error (DNL).................18 Product ID Low Register.................................. 39 Zero Error (ZE).................................................18 Product ID High Register..................................39 Gain Error (GE)................................................ 18 Chip Grade Register.........................................40 Spurious-Free Dynamic Range (SFDR)...........18 Scratchpad Register.........................................40 Effective Number of Bits (ENOB)..................... 18 SPI Revision Register...................................... 40 Total Harmonic Distortion (THD)...................... 18 Vendor ID Low Register................................... 41 Dynamic Range (DR)....................................... 18 Vendor ID High Register...................................41 Signal-to-Noise Ratio (SNR)............................ 18 Stream Mode Register..................................... 41 Signal-to-Noise-and-Distortion (SINAD) Interface Configuration C Register...................42 Ratio...............................................................18 Interface Status A Register.............................. 42 Aperture Delay................................................. 18 Exit Configuration Mode Register.....................42 Transient Response......................................... 18 Averaging Mode Register.................................43 Common-Mode Rejection Ratio (CMRR).........18 Channel 0 Offset Registers.............................. 43 Power Supply Rejection Ratio (PSRR)............ 18 Channel 1 Offset Registers.............................. 44 Theory of Operation.............................................19 Channel 0 Gain Registers................................ 45 Overview.......................................................... 19 Channel 1 Gain Registers................................ 45 Converter Operation.........................................20 Modes Register................................................ 46 Transfer Function............................................. 20 Internal Oscillator Register...............................46 Analog Features...............................................20 Output Driver Register......................................47 Digital Sample Processing Features................ 21 Test Pattern Registers......................................47 Applications Information...................................... 23 Digital Diagnostics Register............................. 48 Typical Application Diagrams........................... 23 Digital Errors Register...................................... 48 Analog Front-End Design.................................24 Outline Dimensions............................................. 49 Reference Circuitry Design ............................. 24 Ordering Guide.................................................49 Device Reset....................................................25 Evaluation Boards............................................ 49 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