8Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
MT41K2G4 256 Meg x 4 x 8 banks
MT41K1G8 128 Meg x 8 x 8 banks
MT41K512M16 64 Meg x 16 x 8 banks
T of 95C
C
Description
64ms, 8192-cycle refresh up to 85C
DDR3L (1.35V) SDRAM is a low voltage version of the
32ms, 8192-cycle refresh at >85C to 95C
DDR3 (1.5V) SDRAM. Refer to a DDR3 (1.5V) SDRAM
Self refresh temperature (SRT)
data sheet specifications when running in 1.5V com-
Automatic self refresh (ASR)
patible mode.
Write leveling
Multipurpose register
Features
Output driver calibration
V = V = 1.35V (1.2831.45V)
DD DDQ
Backward compatible to V = V = 1.5V 0.075V
DD DDQ Options Marking
Supports DDR3L devices to be backward com-
Configuration
patible in 1.5V applications
2 Gig x 4 2G4
Differential bidirectional data strobe
1 Gig x 8 1G8
8n-bit prefetch architecture
512 Meg x 16 512M16
Differential clock inputs (CK, CK#)
FBGA package (Pb-free) x4, x8
8 internal banks
78-ball (9mm x 13.2mm) SN
Nominal and dynamic on-die termination (ODT)
FBGA package (Pb-free) x16
for data, strobe, and mask signals
96-ball (9mm x 14mm) HA
Programmable CAS (READ) latency (CL)
Timing cycle time
Programmable posted CAS additive latency (AL)
1.25ns @ CL = 11 (DDR3-1600) -125
Programmable CAS (WRITE) latency (CWL)
1.07ns @ CL = 13 (DDR3-1866) -107
Fixed burst length (BL) of 8 and burst chop (BC) of 4
Operating temperature
(via the mode register set [MRS])
Commercial (0C T +95C) None
C
Selectable BC4 or BL8 on-the-fly (OTF)
Industrial (40C T +95C) IT
C
Self refresh mode
Revision :A
Table 1: Key Timing Parameters
t t t t
Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns)
1
-107 1866 13-13-13 13.91 13.91 13.91
-125 1600 11-11-11 13.75 13.75 13.75
1. Backward compatible to 1600, CL = 11 (-125).
Note:
09005aef8591dc1f Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
8Gb_DDR3L.pdf - Rev. E 9/18 EN 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.8Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing
Parameter 2 Gig x 4 1 Gig x 8 512 Meg x 16
Configuration 256 Meg x 4 x 8 banks 128 Meg x 8 x 8 banks 64 Meg x 16 x 8 banks
Refresh count 8K 8K 8K
Row address 64K (A[15:0]) 64K (A[15:0]) 64K (A[15:0])
Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0])
Column address 4K (A[13,11, 9:0]) 2K (A[11,9:0]) 1K (A[9:0])
Page size 2KB 2KB 2KB
Figure 1: DDR3L Part Numbers
Example Part Number: MT41K1G8SN-125:A
-
:
Configuration Package Speed Revision
MT41K
^
:A Revision
Temperature
Configuration
Commercial
2 Gig x 4 2G4
None
1 Gig x 8 1G8 Industrial temperature
IT
512 Meg x 16 512M16
Speed Grade
t
Package Mark -125
CK = 1.25ns, CL = 11
78-ball 9.0mm x 13.2mm FBGA SN t
-107 CK = 1.07ns, CL = 13
96-ball 9.0mm x 14.0mm FBGA HA
Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on