256M DDR2 -AS4C16M16D2 Revision History AS4 D - -ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet D 201 O O L D Q F H 0 H P R U , Q F 7 D O R U : D 6 D Q & D U O R V & 7 ( / ) O O L D Q F H 0 H P R U , Q F U H V H U Y H V W K H U L J K W W R F K D Q J H S U R G X F W V R U V S H F L I L F D W L R Q Z L W K R X W Q R W L F H Confidential - 1/66 - Rev.1.0 May 2015256M DDR2 -AS4C16M16D2 16M x 16 bit DDRII Synchronous DRAM (SDRAM) &RQILGHQWLDO Advanced (Rev. 1.0, Ma / 201 ) Features - ( ( & 6 W D Q G D U G & R P S O L D Q W 3 U R J U D P P D E O H 0 R G H ( W H Q G H G 0 R G H U H J L V W H U V - ( ( & V W D Q G D U G 9 , 2 6 6 7 / B F R P S D W L E O H 3 R V W H G & 6 D G G L W L Y H O D W H Q F / : 5 , 7 ( O D W H Q F 5 ( O D W H Q F W 3 R Z H U V X S S O L H V 9 9 9 9 4 & . 2 S H U D W L Q J W H P S H U D W X U H % X U V W O H Q J W K R U &RPPHUFLDO CCa % X U V W W S H 6 H T X H Q W L D O , Q W H U O H D Y H ,QGXVWULDO Ca C / / H Q D E O H G L V D E O H 6 X S S R U W V - ( ( & F O R F N M L W W H U V S H F L I L F D W L R Q 2 I I & K L S U L Y H U 2 & ) X O O V Q F K U R Q R X V R S H U D W L R Q , P S H G D Q F H G M X V W P H Q W G M X V W D E O H G D W D R X W S X W G U L Y H V W U H Q J W K ) D V W F O R F N U D W H 0 + 2 Q G L H W H U P L Q D W L R Q 2 7 L I I H U H Q W L D O & O R F N & . & . 5 R + 6 F R P S O L D Q W % L G L U H F W L R Q D O V L Q J O H G L I I H U H Q W L D O G D W D V W U R E H 4 6 4 6 X W R 5 H I U H V K D Q G 6 H O I 5 H I U H V K L Q W H U Q D O E D Q N V I R U F R Q F X U U H Q W R S H U D W L R Q U H I U H V K F F O H V P V YHUDJH UHIUHVK SHULRG E L W S U H I H W F K D U F K L W H F W X U H V C 7& C , Q W H U Q D O S L S H O L Q H D U F K L W H F W X U H V C 7& 5C 3 U H F K D U J H D F W L Y H S R Z H U G R Z Q 3 D F N D J H E D O O P P P D ) % * 3 E ) U H H D Q G + D O R J H Q ) U H H Confidential - 2/66 - Rev.1.0 May 2015