A4915
3-Phase MOSFET Driver
DESCRIPTION
FEATURES AND BENEFITS
5 to 50 V supply voltage
The A4915 is designed for pulse width modulated (PWM)
Latched TSD with fault output
current control of 3-phase brushless DC motors. The A4915
Drives six N-channel high current MOSFETs
is capable of high current gate drive for 6 all N-channel power
Internally controlled synchronous rectification
MOSFETs. An internal charge pump ensures gate drive down
Speed voltage input enables internal PWM duty cycle
to 7 V supply and provides limited gate drive down to 5 V. A
control of full bridge
bootstrap capacitor is used to generate a supply voltage greater
Center aligned PWM
than the source voltage of the high side MOSFET, required
Internal UVLO and crossover current protection
for N-channel MOSFETs.
Hall switch inputs
Internal synchronous rectification control circuitry is provided
Adjustable dead time protection
to improve power dissipation in the external MOSFETs during
Low power sleep mode for battery-powered applications
PWM operation. Internal circuit protection includes latched
PACKAGES:
thermal shutdown, dead time protection, and undervoltage
lockout. Special power up sequencing is not required.
The A4915 is supplied in a 28-pin TSSOP with an exposed
28-pin TSSOP
28-contact QFN
thermal pad (suffix LP) and a 28-contact 5 5 mm QFN with
with exposed thermal pad
5 mm 5 mm 0.90 mm
an exposed thermal pad (suffix ET). These packages are lead
(LP package)
(ET package)
(Pb) free, with 100% matte-tin leadframe plating.
Not to scale
Functional Block Diagram
0.47 F
VDD A4915
VBB V
IN
Comm Charge Pump
HA
47 V
CREG
Logic Regulator CVBB1
CVBB2
TVS
HB
VREG
HC
VDD
VDD
Phase A
Bootstrap
R2
CVDD1
Monitor R1
R3
HA
CA
HB
C
CB BOOTA HC
TDEAD
High Side
CC
Driver
See Note 1
BRAKEn
GHA
R R
dead DIR GHB GATE
GHC
Control
ENABLE
SA
Logic
SB
VREG
SC
To Phase B
GLA
OSC
To Phase C
GLB R
GATE
Low Side GLC
VDD
Voltage to
Driver
One of three phases shown
SPEED
Duty
V LSS
RESET
GND
FAULT
Note 1: Allegro-recommended Hall latches: APS13290 and APS13291.
A4915-DS, Rev. 5 July 27, 2018
MCO-0000484
CP2
CP1A4915 3-Phase MOSFET Driver
SELECTION GUIDE
Part Number Package Packing*
28-contact QFN with 1500 pieces
A4915METTR-T
exposed thermal pad per 7-in. reel
28-pin TSSOP with 4000 pieces
A4915MLPTR-T
exposed thermal pad per 13-in. reel
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Unit
Load Supply Voltage V 0.3 to 50 V
BB
Logic Supply Voltage V 0.3 to 6 V
DD
VREG Pin V 0.3 to 16 V
REG
CP1 Pin V 0.3 to 16 V
CP1
V 0.3 to
CP1
CP2 Pin V V
CP2
V + 0.3
REG
Logic Inputs V 0.3 to 6 V
I
Hall Inputs V 0.3 to 6 V
Hx
Logic Outputs V 0.3 to 6 V
O
SPEED Input V 0.3 to 6 V
SPEED
0.3 to
CA, CB, and CC Pins V V
Cx
V + 50
REG
V 16 to
Cx
GHA, GHB, and GHC Pins V V
GHx
V + 0.3
CX
V 16 to
Cx
SA, SB, and SC Pins V V
Sx
V + 0.3
Cx
GLA, GLB, GLC Pins V V 16 to 18 V
GLx REG
LSS Pin V V 16 to 18 V
LSS REG
Maximum Continuous Junction
T (max) 150 C
J
Temperature
Storage Temperature Range T 55 to 150 C
stg
Operating Ambient Temperature
T 20 to 105 C
A
Range
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
Package ET, on 4-layer PCB based on JEDEC standard 32 C/W
Package Thermal Resistance R
JA
Package LP, on 4-layer PCB based on JEDEC standard 28 C/W
*Additional thermal information available on the Allegro website.
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com