ADVANCED LINEAR ALD500AU/ALD500A/ALD500 DEVICES, INC. PRECISION INTEGRATING ANALOG PROCESSOR APPLICATIONS BENEFITS 4 1/2 digits to 5 1/2 digits plus sign measurements Wide dynamic signal range Precision analog signal processor Very high noise immunity Precision sensor interface Low cost, simple functionality High accuracy DC measurement functions Automatic compensation and cancellation of Portable battery operated instruments error sources Computer peripheral Easy to use to acquire true 18 bit,17 bit, or PCMCIA 16 bit conversion and noise performance Inherently linear and stable with temperature and component variations GENERAL DESCRIPTION The ALD500AU/ALD500A/ALD500 are integrating dual slope analog FEATURES processors, designed to operate on 5V power supplies for building precision analog-to-digital converters. The ALD500AU/ALD500A/ Resolution up to 18 bits plus sign bit ALD500 feature specifications suitable for 18 bit/17 bit/16 bit resolution and over-range bit conversion, respectively. Together with three capacitors, one resistor, Accuracy independent of input source a precision voltage reference, and a digital controller, a precision impedances 12 Analog to Digital converter with auto zero can be implemented. The High input impedance of 10 Inherently filters and integrates any digital controller can be implemented by an external microcontroller, external noise spikes under either hardware (fixed logic) or software control. For ultra high resolution applications, up to 23 bit conversion can be implemented with Differential analog input an appropriate digital controller and software. Wide bipolar analog input voltage range 3.5V The ALD500 series of analog processors accept differential inputs and Automatic zero offset compensation the external digital controller first counts the number of pulses at a fixed Low linearity error - as low as 0.002% clock rate that a capacitor requires to integrate against an unknown Fast zero-crossing comparator - 1s analog input voltage, then counts the number of pulses required to Low power dissipation - 6mW typical deintegrate the capacitor against a known reference voltage. This Automatic internal polarity detection unknown analog voltage can then be converted by the microcontroller Low input current - 2pA typical to a digital word, which is translated into a high resolution number, Microprocessor controlled conversion representing an accurate reading. This reading, when ratioed against Optional digital control from a microcon- the reference voltage, yields an accurate, absolute voltage measurement troller, an ASIC, or a dedicated digital circuit reading. Flexible conversion speed versus resolution trade-off The ALD500 analog processors consist of on-chip digital control circuitry to accept control inputs, integrating buffer amplifiers, analog switches, PIN CONFIGURATION and voltage comparators. It functions in four operating modes, or phases, namely auto zero, integrate, deintegrate, and integrator zero ALD500 phases. At the end of a conversion, the comparator output goes from high to low when the integrator crosses zero during deintegration. ALD500 analog processors also provide direct logic interface to CMOS + C 1 16 V INT logic families. - V 2 15 DGND C 3 14 AZ C ORDERING INFORMATION OUT B B 4 13 Operating Temperature Range * UF 0C to +70C0C to +70C0C to +70C AGND 5 12 A 16-Pin 16-Pin 16-Pin Wide Body - + C 6 11 V REF IN Plastic Pin Small Outline Small Outline + C - 7 10 V REF IN Package Package (SOIC) Package (SOIC) - + V 8 9 V REF REF ALD500PC (16 bit) ALD500SC (16 bit) ALD500SWC (16 bit) ALD500APC (17 bit) ALD500ASC (17 bit) ALD500ASWC (17 bit) ALD500AUPC (18 bit) ALD500AUSC (18 bit) ALD500AUSWC (18 bit) PC, SC, SWC PACKAGE Contact factory for industrial temperature range * Rev. 1.02 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 FIGURE 1. ALD 500 Functional Block Diagram R C C REF INT INT C AZ + - C + V V - INT C REF REF C BUF C REF REF AZ (9) (8) (1) (4) (7) (6) (3) SW SW R R - SW IN Buffer Integrator + + V IN - (11) + - + SW SW R R + - Comp1 - Level Comp2 C OUT Shift + (14) SW AZ + - SW SW SW R R S SW Az Polarity DGND Detection AGND (15) (5) SW IN SW G - V IN Analog Phase (10) Switch Decoding Control Logic Signals V V A B SS DD (2) (16) (12) (13) Control Logic GENERAL THEORY OF OPERATION c. Offset voltage values of the analog components, such Dual-Slope Conversion Principles of Operation as V , are cancelled out and do not affect accuracy. X The basic principle of dual-slope integrating analog to digital d. Accuracy of the system depends mainly on the accuracy converter is simple and straightforward. A capacitor, C , is and the stability of the voltage reference value. INT charged with the integrator from a starting voltage, V , for a X fixed period of time at a rate determined by the value of an e. Very high resolution, high accuracy measurements unknown input voltage, which is the subject of measurement. can be achieved simply and at very low cost. Then the capacitor is discharged at a fixed rate, based on an external reference voltage, back to V where the discharge An inherent benefit of the dual slope converter system is noise X time, or deintegration time, is measured precisely. Both the immunity. The input noise spikes are integrated (averaged to integration time and deintegration time are measured by a near zero) during the integration periods. Integrating ADCs digital counter controlled by a crystal oscillator. It can be are immune to the large conversion errors that plague demonstrated that the unknown input voltage is determined successive approximation converters and other high resolution by the ratio of the deintegration time and integration time, and converters and perform very well in high-noise environments. is directly proportional to the magnitude of the external reference voltage. The slow conversion speed of the integrating converter provides inherent noise rejection with at least a 20dB/decade attenuation The major advantages of a dual-slope converter are: rate. Interference signals with frequencies at integral multiples a. Accuracy is not dependent on absolute values of of the integration period are, theoretically, completely removed. integration time t and deintegration time t , but is Integrating converters often establish the integration period to INT DINT dependent on their relative ratios. Long-term clock frequency reject 50/60Hz line frequency interference signals. variations will not affect the accuracy. A standard crystal controlled clock running digital counters is adequate to generate The relationship of the integrate and deintegrate (charge very high accuracies. and discharge) of the integrating capacitor values are shown below: b. Accuracy is not dependent on the absolute values of R C . as long as the component values do not vary V = V - (V t / R C ) INT and INT INT X IN INT INT INT through a conversion cycle, which typically lasts less than 1 second. 2 Advanced Linear Devices ALD500AU/ALD500A/ALD500