Dear customer st LAPIS Semiconductor Co., Ltd. LAPIS Semiconducto), on the 1 day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (LAPIS Technology) and LAPIS Technology succeeded LAPIS Semiconductors LSI business. Therefore, all references toLAPIS Semiconductor Co., Ltd,LAPIS Semiconducto and/orLAPI in this document shall be replaced withLAPIS Technology Co., Ltd Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDL630Q464-01 Issue Date: Oct. 26, 2016 ML630Q464/Q466 Ultra Low Power 32-bit Microcontroller GENERAL DESCRIPTION TM This LSI is a high-performance low power 32-bit microcontroller. Equipped with a 32-bit CPU core Cortex -M0+, it implements a 128 KB flash memory, 16 KB RAM, rich peripheral circuits, such as USB Full speed device, synchronous serial 2 port, UART, I C bus interface, supply voltage level detect circuit, RC oscillation type A/D converter, successive approximation type A/D converter, and LCD driver. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) is most suitable for battery-driven applications. FEATURES CPU TM 32-bit RISC CPU (CPU name: ARM Cortex -M0+) Thumb /Thumb -2 instruction supported Serial Wire Debug Port Minimum instruction execution time 30.5 s ( 32.768 kHz system clock) 41.7ns ( 24 MHz system clock) Internal memory Re-writing the program memory area by software Number of segments Flash memory Product name SRAM Program area Data area ML630Q464 64KB (16K 32bit) 2KB (0.5K 32bit) 8KB (2K 32bit) ML630Q466 128KB (32K 32bit) 2KB (0.5K 32bit) 16KB (4K 32bit) Interrupt controller (NVIC) 1 non-maskable interrupt source (Internal source: 1) 31 maskable interrupt sources (Internal sources: 30, External sources: 1) Priority level (4-level) can be set for each interrupt DMA controller (DMAC) 2 channels Enable to allocate multiple DMA transfer request sources for each channel. Channel priority: fixed mode/round robin mode DMA transfer mode: cycle steal mode/burst mode DMA request type: software requests/hardware requests Maximum transfer count: 65,536 Data transfer size: 8 bits/16 bits/32 bits Transfer request source: SSIOF, UART, UARTF, I2CF, RC-ADC, SA-ADC Time base counter (TBC) Low-speed time base counter 1 channel 1 kHz Timer 10 Hz / 1 Hz interrupt function 1/37