HV257 32-Channel High-Voltage Sample-and-Hold Amplifier Array Features General Description Thirty-two Independent High-voltage Amplifiers The HV257 is a 32-channel, high-voltage sample-and-hold amplifier array integrated circuit. It 300V Operating Voltage operates on a single high-voltage supply, up to 300V, 295V Output Voltage and two low-voltage supplies, V and V . DD NN 2.2V/s Typical Output Slew Rate All 32 sample-and-hold circuits share a common Adjustable Output Current Source Limit alog input, V . The individual sample-and-hold an SIG Adjustable Output Current Sink Limit circuits are selected by a five-to-32 logic decoder. The Internal Closed-loop Gain of 72V/V sampled voltage on the holding capacitor is buffered by 12 M Feedback Impedance a low-voltage amplifier and is magnified by a high-voltage amplifier with a closed-loop gain of 72V/V. Layout Ideal for Die Applications The internal closed-loop gain is set for an input voltage range of 0V to 4.096V. The input voltage can be up to Applications 5V, but the output will saturate. The maximum output Microelectromechanical Systems (MEMS) Driver voltage swing is 5V below the V high-voltage supply. PP The outputs can drive capacitive loads of up to Piezoelectric Transducer Driver 3000 pF. Optical Crosspoint Switches (Using MEMS Technology) The maximum output source and sink current can be adjusted by using two external resistors. An external resistor controls the maximum sourcing R SOURCE current, and an external R resistor controls the SINK maximum sinking current. The current limit is approximately 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low-voltage silicon junction diode is made available to help monitor the die temperature. Package Type 100-lead MQFP (Top view) 100 1 See Table 3-1 for pin information. 2017 Microchip Technology Inc. DS20005827A-page 1HV257 Functional Block Diagram BYP-VPP BYP-AVDD BYP-AVNN Anode Cathode To internal VPP bus VPP To internal analog VDD bus AVDD Bias Circuit To internal analog VNN bus AVNN To internal digital VDD bus DVDD DVNN To internal digital VNN bus AV DD V + PP VSIG DV + DD - C H HV 0 - OUT Q 0 AV NN Q 1 AV NN S/H-0 A 0 71R A R 1 A 2 5 to 32 AV DD A Decoder 3 V + PP A 4 + - C H HV 1 - OUT EN AV NN Q 31 AV NN S/H-1 DGND 71R R AGND AV DD V HV + OUT PP To all HV Current OUT RSOURCE + Source amplifiers - C H Limiting HV 31 - OUT AV NN AV HV NN OUT S/H-31 To all HV Current OUT RSINK Sink 71R amplifiers R Limiting DS20005827A-page 2 2017 Microchip Technology Inc.