NFC-TAG-MN63Y1213-2020

Sep.5th,2013 Evaluation board circuit diagram Evaluation board circuit diagram Evaluation board circuit diagram and implementation and implementation and implementation MN63Y1212/1213 MN63Y1212/1213 MN63Y1212/1213 Ver. 1.0 th Sep.5 ,2013 Semiconductor Business Group Industrial Devices Company Panasonic Corporation2 MN63Y1212/1213 Pin layout Sep.5th,2013 V N V N D I D S S I D N N R D D C R A C C Q A A L Q 8 7 6 5 8 7 6 5 MN63Y1212 MN63Y1213 TOP VIEW TOP VIEW 1 2 3 4 1 2 3 4 V N V V V V V V B C S A B D S A S D S E X Name Pin No. Input/Output IO type Function MN63Y1212 MN63Y1213 1 VB VB I/O --- Coil terminal MN63Y1212: Open or Connect to Ground 2 N.C. VDDEX --- --- / Power MN63Y1213: External Power Supply 3 VSS VSS --- GND Ground 4 VA VA I/O --- Coil terminal USE : Pull up to VDD 5 NIRQ NIRQ Output Open Drain NOT USE : Open or Connect to Ground (same as Pin No.2) MN63Y1212: Open or Connect to Ground (same as Pin No.2) 6 N.C. SCL --- / Input --- / Open Drain MN63Y1213: I2C Clock input MN63Y1212: Open or Connect to Ground (same as Pin No.2) 7 N.C. SDA --- / I/O --- / Open Drain MN63Y1213: I2C Data input/output Internal analog power supply 8 VDDA VDDA --- Power (Connect a capacitor between this pin and VSS shortest as possible.)